mallikmarasu
Member level 3
Hi please post good veriog questions here .That can helpful to everyone to update
our knowledge dailybasis.
Here i am posting some questions today.
1. What is the use of "wait" statement in verilog.Where we can use this statement
in verilog program.
2. What is the difference between "wait " and "while " statement.
3. Below i have given some statements .Describe each statement whether
simulation tool will give either error or warning or no warning.
(a) A number has been assigned that is larger than the number of bits
allocated to it. means 2'd27
(b) The port sizes for the module instance and definition do not match.
(c) A number is assigned to a variable that has too little memory allocated to
store it.
(d) A negative number is assigned to a register.
(e) Bits outwith the size of a variable are being accessed.
our knowledge dailybasis.
Here i am posting some questions today.
1. What is the use of "wait" statement in verilog.Where we can use this statement
in verilog program.
2. What is the difference between "wait " and "while " statement.
3. Below i have given some statements .Describe each statement whether
simulation tool will give either error or warning or no warning.
(a) A number has been assigned that is larger than the number of bits
allocated to it. means 2'd27
(b) The port sizes for the module instance and definition do not match.
(c) A number is assigned to a variable that has too little memory allocated to
store it.
(d) A negative number is assigned to a register.
(e) Bits outwith the size of a variable are being accessed.