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constraints in implementation by ise

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ahmadagha23

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Hi,
1- Can I specify the mapped package pins for ports in VHDL code only in .UCF file? can you write its instruction and the steps of adding this file to my design? Is it possible to implement my design and configure my FPGA board without declaring any .ucf file?

2- what is the difference between synplifypro and ise constraints?

regards
 

for ise, the only way to map the package pins to vhdl ports is ucf. the ucf contains many constraints i think u need just "the pin assignment constraints". simply select the top level file of ur project, go to the processes window, expand the tree of "user constraints" and double click on "assign package pin (PACE)". it's a gui tool that is very easy to use. the ucf will created automatically.
 

one more option is directly including ur UCF file from ADD FILE option...but tht requires a prior knowledge of how to write constraints in UCF file (text format)....
i suppose GUI option will b better for U as u r doing it for the 1st time...

no idea abt synplifypro as i've never worked on it...
 

If you don't want to use a UCF file, you may be able to specify your Xilinx constraints as VHDL attributes. However, some constraints don't work in HDL.

I'm no VHDL expert, but this example seems to work in ISE XST. It's a 4-bit counter with LOC pin location constraints, and a clock PERIOD timing constraint.
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is
  port
  (
    CLK : in  std_logic;
    Q   : out std_logic_vector(3 downto 0)
  );
  attribute PERIOD : string;
  attribute PERIOD of CLK : signal is "50 MHz";
  attribute LOC : string;
  attribute LOC of CLK : signal is "C10";
  attribute LOC of Q   : signal is "E1 E2 E3 E4";
end top;

architecture archi of top is
  signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
  process (CLK)
  begin
    if (rising_edge(CLK)) then
      tmp <= tmp + 1;
    end if;
  end process;
  Q <= tmp;
end archi;
I don't know about Synplify Pro.
 

oh, it's good for me too!
thk u x mas!
 

also recommend that when using the ISE pin placement GUI that you check the UCF before and after to get an idea of what it did and the format that the UCF has
 

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