Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to simulate capacitor mismatch of a pipeline SH circuit?

Status
Not open for further replies.

didibabawu

Member level 5
Joined
Dec 21, 2005
Messages
90
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,286
Activity points
1,851
sh capacitor

I'm now designing a SH circuit of a 8bit pipelined ADC. I know the capacitor mismatch is a very important consideration of a ADC. But I don't know how to simulate the capacitor mismatch. should I use monte carlo? and how ?

Thank you very much.
 

capacitor mismatch effect in adc

The simulation can not get the capacitor mismatch value. You can do a post layout extraction. From the extraction netlist, you can find the mismatch value.
 

capacitor mismatch layout

To bigpop, cap mismatch doesn't source from layout even if post layout extraction obtains different parasitic capacitance for two caps.

Added after 21 minutes:

Generally, cap mismatch doesn't affect SH circuit much, but not multiplying DAC in pipeline ADC design. Some modeling can used to evaluate cap mismatch.
 

mimcap mismatch

a document can be obtained from foundry when a project is begun. DNL and INL of ADC can be estimated. Architecture of ADC is sure.
 

montecarlo analysis for mismatch in a capacitor

I only manul calculate the mismatch effact base on foundry's matching table. never do simulation about mismatch.
 

Re: how to simulate capacitor mismatch of a pipeline SH circ

if this mismatch comes from process variation, post layout simulation can not give you help on this mismatch effect. I always calculate manully. you could get a mismatch report from foundry and use sigma data to calculate
 

By using the ideal amp,then run mento-carlo analysis, you can get the sigma of delta(c)/c. I guess.
 

If it is modelled monte-carlo has an mismatch option next to the corner option. Otherwise hand calculate your worst case capacitors and simulate with those values. Preferably you should do both to get a sanity check on both methods.
 

#1 Calculate the caps mismatch from foundry's matching table.
#2 Put this value, for example, a small cap represent the mismatch into your simulation
 

Re: how to simulate capacitor mismatch of a pipeline SH circ

I have used the following two ways

1.a. obtain mismatch data from foundry or by looking at your models for capacitors of that size.
1.b model the switch cap section in matlab and run full montecarlo to see affect of mismatch
1.c use information to evaluate if smaller/larger sizes need to be used.

2.a run montecarlo in simulator environment
2.b braid hair while waiting for sims to finish
2.c write that great [insert country here] novel you've always been wanting to write
2.d teach self foreign language
2.e examine finished sim results respond similarly as 1.c

I recommend the #1 approach, personally.
 

Re: how to simulate capacitor mismatch of a pipeline SH circ

Dear didibabawu....

Even though it's toolate...

firstly in ur schematic replace the Capacitor,Resistor,MOStransistors which u used with mismatch model..

Ex: if ur using mimcap there will be another model with the name mimcap_mis.

the remaining things are very simpler...u can even get from cadence help doc...

it would be regarding how to monte carlo.....


Hope this could give u some idea....coz i have done lot of monte carlo simulation for different analog systems...
 

    didibabawu

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top