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SELW RATE IN THE FALLING EDGE

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kanounmoez

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hi,
i have to design a OP AMP with fast slew rate. i hve selecte the Miller OTA architecture and i have calculate the current that can give me a slew rate of 1v/12.5ns. my problem is when i have done a simulation, the slew rate in the rising edge is like my spec but the slew rate in the falling edge is not equale to those in rising edge.
some one can help me.
i want to understand this difference in the slew rate and how can i improve my slew rate in the falling edge.
thanks
 

Hi
Is your circuit symmetric?
Please sketch your schematic.
regards
 

HI,

Maybe you can use differential opamp.

AhQ
 

As I sad, I have to design an integrator followed by differential ended amplifier followed by an ADC with 45MHz frequency.
My differential ended amplifier should have a Slew Rate of 1V/12.5ns. I seen in a paper (Z. Czarnul, Design of fully balanced analog systems based on ordinary and/or modified single ended opamps) that I can design it by taken a single ended OP AMP and doing some modifications to obtain fully balanced differential ended amplifier.
When i have design my single ended, the slew rate in the rising edge is like my specification (1V/12.5ns) but the one in falling edge is very different.
you can find here my design
thanks
 

From your schematic, the rising edge is different from the falling edge. at the falling edge, the sink current is limited by the nmos current mirror
 

can you explain more please
thanks
the current in the dif paire is 750uA and the one in the second stage is 2mA
 

Hi
As I said your circuit is not symmetric.
see M3 and M4.

what is functionality of M11 and M21?

regards
 

no, my circuit is fully balanced differential ampli.
M21 and M22 is a CMFB. normaly the output is connected via a resistor to the OCM.
 

Hi
This is a single ended opamp.
what is the meaning of CMFB?
M6 can set the drain of M4 and so we dosn't need CMFB.
regards
 

I think reza is saying, by unbalanced, that your falling slew rate is limited by the current mirror.

In other words: Your spec is 1V/12.5ns, which equals 80MV/sec.
But with 2mA into a 26pF load (higher with the parasitics), you only get:
2mA/26pF = 77MV/sec.
This will be worse with the parasitics of your output devices and your compensation cap.

Boost the 2mA higher (3mA or so) and you'll be fine.
 

    K

    kanounmoez

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thanks,
but i think that tha slew rate have to be calculated for I5 and Cc? not Cload.
another think, imagine that my opamp is followed with an ADC that have an input capacitance of 3 pf// with a resistor of 100M. the ADC have a sampling frequency of 50 MHZ and i would like to design an antialiasing filter:
opamp-antialiasing filter- ADC.
what shoul be the capacitance load for my opamp???
 

First, note again that the slew rate is *NOT* symmetric. Therefore, you have a different calculation for the slew rate going high versus the slew rate going low. run some experiments in simulation to get a feel for this.

Second, the load should be the first thing you determine for design of an opamp. Combine the filter and the ADC, and make a simple RC model for the equivalent load of these blocks. Then do a first pass design with these reqirements. Finally, simulate everything together to verify.
 

    K

    kanounmoez

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ok, thank you very much
haw can i calculat the equivalent noise and how can i choose the specification of my antialiasing filter.
in the case where my ADC present 3pf/100MOhms input and 50MHz sampling frequency how can i choose my my low pass filter. Fs/2=1/(2*pi*RC)??
and then, how can i calculat the equivalent capacitance load?
thank you
 

I think the reason for slow negative going slew rate is the parastic capacitance at the drain of M51 or M512.

you should simulate it to satisfy the spec.
 

thanks for all person who help me
i find a paper that explain the difference betwen SR+ and SR- and the relation betwen I1 and I2 to have the same SR.
 

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