Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Three synthesis problems

Status
Not open for further replies.
D

doreen105

Newbie level 6
Joined
Jun 4, 2007
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Beijin ,China
Activity points
1,397
Hello everyone,I have some problems of synthesis,thanks for help

1)I use RTL compiler without GUI,I need to set pathdelay,how can I get the paths information?For example,there are A,B,C,D register in the design.And there is a path between A and B,but no path between C and D.How can I know?Just from the RTL netlist???

2)Should I set constraint for every path?

3)what constraints should be provided by the foundary ?
 

Re: synthesis problem

1)You can trace the path using a tools like verdi. In DC, you can use command like get_timing_path to check it.
2)It should depends on your design purpose.
3)Constraint should depends on your design purpose, but not the fondary.
 

Re: synthesis problem

For 1,what do you mean by there is no path? are your referring to the timing information ? If timing information is missing, then in magma env, you can query for the timing information on that particular register. If you want to check for datapath between C and D, you can either write a simple perl script to see if there is any connection between C and D. It is very easy to debug if you are in magma synthesis env as its datamode is very powerful.

yes, your design should be constrained completely unless you are very sure that the ignored path is never exercised.

ur .lib will be provided by ur vendor/foundry. They will contain the env (PVT ) conditions for the given process. Rest are all design dependent .


doreen105 said:
Hello everyone,I have some problems of synthesis,thanks for help

1)I use RTL compiler without GUI,I need to set pathdelay,how can I get the paths information?For example,there are A,B,C,D register in the design.And there is a path between A and B,but no path between C and D.How can I know?Just from the RTL netlist???

2)Should I set constraint for every path?

3)what constraints should be provided by the foundary ?
Click to expand...
 

synthesis problem

In rtlcompiler first check the path's are available by report timing -from A -to B
then apply the constraint.
whatever mistake or wrong constraint you applied in rtlcompiler.report timing -lint will give you clear idea.

Thanks
aravind
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top