Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help needed in the field of comparator design

Status
Not open for further replies.

jiangnancai

Junior Member level 3
Joined
Sep 3, 2006
Messages
31
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,433
I'm designing a dynamic comparator these days,whose spec is as follows:

The resolution: 4mv
Speed: 5Mhz

Generally,comparator has two types of topolgy.
The first is open-loop amplifier,which is limited by its speed. So I use the second architecture: Preamplifier + Latch.

Now the simulation results show that the comparator can detect an input difference
voltage of 1mv. However I hadn't simulate the offset voltage .

My question is that:

How can I see the offset voltage.
If the offset voltage is larger than 1mv( resolution), then will it damage the comparator's resolution in the actually-operated comparators?
The last question is how can i solve this problem? The zuto-zero calibration for offset voltage???

Thanks a million~~:D
 

Well, your offset voltage is going to be mainly from mismatch in your preamplifier. It depends on layout, size of the devices on your amplifier and process. You didn't say what process you are using, but as an example, for CMOS process, Vt offset is usually in the form of (Vmismatch/sqrt(W*L)), where W & L is width and lenght of your transistor and Vmismatch is a process dependent value. You size up your transistor until you meet your mismatch target or you can calibrate the offset voltage out as your suggest. Another popular way to lower offset is to chop the input, but this limits your speed.

You can simulate with offset by putting a voltage source with the expected offset value in series with the input on one of the input or use monte-carlo simulation.
 

If you don't use the offset cancel circuits, calculate the pre_amplifier offset is enough. The match table you can apply from foundry. Rowokii's reply is very well.you can reference his reply and match table, then you can calculate the offset value.
 

Thanks for the above suggestions~.

I use the tsmc CMOS process now

It is said that latch stage is high resolution but high offset voltage too. Is this description true?

Second, by add a preamplifier stage,the offset of the latch can be reduced by the gain of preamp. So the offset of the preamp becomes critical!

What i want to know is the feasibility that by increasing the W.L to reduce the preamp's offset to less than 4mv. I have no experience about this,but i want to know a general idea. I think the auto-zero calibration technique is too complicated for it needs two clock signal to control.
Any good idea or suggestions?
 

jiangnancai said:
It is said that latch stage is high resolution but high offset voltage too. Is this description true?

Second, by add a preamplifier stage,the offset of the latch can be reduced by the gain of preamp. So the offset of the preamp becomes critical!

What i want to know is the feasibility that by increasing the W.L to reduce the preamp's offset to less than 4mv.

latch stage is high resolution but high offset voltage too. That is right.
Second, by add a preamplifier stage,the offset of the latch can be reduced by the gain of preamp. So the offset of the preamp becomes critical!
Yes. you are right.
you can reduce the offset by increasing the W.L, but that need large size. The offset as Vt and W/l mismatch. You can calculate offset voltage base on foundry's matching table.
 

Yes,I do the Montl-Carlo analysis today.
In my comparator I use 3stage preamplifiers to trade-off the Gain-Bandwidth limitation.
The Montl-Carlo simulation results shows that the parameter SIGMA is 550uv. I think it is a very small offset , really?? Is it reasonable??
By the way ,I choose the L=5u,W=60u of the preamplifier's critical transistors.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top