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lateral BJT and pch MOSFET in CMOS

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020170

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following picture shows lateral BJT under CMOS process.

In P-substrate CMOS process, to make lateral BJT cause to make parasitic

vertical BJT.

I wonder "why PMOS TR is biased by high voltage?"

If I want to make lateral BJT, I don't have to make P mos TR.

But PMOS TR exists and I have to appliy high voltage.

why PMOS TR is biased by high voltage? If I don't, lateral BJT is not formed?
 

1. If PMOS is biased low voltage - emitter and collector shorted over channel of PMOS
2. As standard CMOS process self-aligned, you can make lateral PNP transistor only through PMOS precisely to supervise width of base.
 

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    020170

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Hello,

If we leave the gate open, the bjt's still be there.
But when we bias it at higher voltage,
that would change Fermi-level under the gate,
making hole injection from emitter easier into base region.
Hence one might observe enhenced current gain...
 

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