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What are the advantages and disadvantages of stack via in layout?

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penchal_gv

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Hi Friends,
What are the advantages & disadvantages of stack via in layout?
 

Stack Via

Do you mean stacking via1 (between metal1 and metal2) and via2 (between metal2 and metal3)?
 

Re: Stack Via

Yes, generally (in new technologies) we place one via over other via, for e.g via1 over via2.
what r advantages n disadvantages by placing like that (stacked via).
 

Stack Via

Well, the obvious advantage is more compact routing: less chip area and less parasitics. Using stacked vias near gates can introduce a little bit more stress, but usually, if the process allows for stacked vias, there are mostly advantages
 

Stack Via

Advantages:
In the bond pad structures, stacked vias are used to provide support for the thicker copper metal lines running above. This is also known as CLVS (Copper line Via Support) structure and is a necessity in sub 90nm bond pad structures.

Disadvantages:
I cannot think of any except for the sole reason that it might affect mask making in some ways or the other.
 

Stack Via

One disadvantage:
large resistance if you use small number of vias
 

Stack Via

I know that in case of larger number of vias it is recommended to stagger them due to stress on metals. So place M1 and M2 offsett and M3 again on M1 etc.
 

Re: Stack Via

Teddy said:
I know that in case of larger number of vias it is recommended to stagger them due to stress on metals. So place M1 and M2 offsett and M3 again on M1 etc.
Click to expand...

Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:

--Cmos_Dude
 

Re: Stack Via

cmos_dude said:
Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:

--Cmos_Dude
Click to expand...

Where did you come across saying that stacking vias this way add stress?
 

Re: Stack Via

srieda said:
cmos_dude said:
Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:

--Cmos_Dude
Click to expand...

Where did you come across saying that stacking vias this way add stress?
Click to expand...


I was just referring to what Teddy had written. But I did encounter the DFM guideline while doing layouts wherein I was not supposed to stack more than three layers of vias.

--Cmos_Dude
 

Re: Stack Via

cmos_dude said:
srieda said:
cmos_dude said:
Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:

--Cmos_Dude
Click to expand...

Where did you come across saying that stacking vias this way add stress?
Click to expand...


I was just referring to what Teddy had written. But I did encounter the DFM guideline while doing layouts wherein I was not supposed to stack more than three layers of vias.

--Cmos_Dude
Click to expand...

I think you were referring to this one....

solidstate said:
Well, the obvious advantage is more compact routing: less chip area and less parasitics. Using stacked vias near gates can introduce a little bit more stress, but usually, if the process allows for stacked vias, there are mostly advantages
Click to expand...

using stacked vias near gates causes stress on the gates and not on the metal layers...
 

Re: Stack Via

advantage is it reduces area of the metal and provides more free space for routing, as we can stack different vias one above the other.

disadvntage is if we are placing all the vias at the same place, one above the other each time during fabrication we will have to etch the same place and this can create aproblem if any one of the vias fail during fabrication time.
therefore every foundary doesnot give this feature.

i will suggest to use more than 1 via of 1 kind, i.e. 2 or via1 then 2 or more via2 over it and the same way for others.
 

Re: Stack Via

advantage: Save area
 

Re: Stack Via

what is Stagger via ?
 

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