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u are going to give u r RTL and constraints as inputs to the tool but along with these to inputs ur also going to give librery file as inputs.
first synthesis tool will use some the algorithm already defined in it from there it will try to convert your RTL to gates which are already defined in the library.
let me know if you need more explanation
you write what is called RTL code in an HDL
putting in mind certain rules and guides to follow in order to have good results in synthesis (meaning not having inferred elements)...
then the synthesizer converts the HDL code to gate level netlist
but u have to give the synthesizer (along with the HDL code), the different constraints for your design and the library of cells you'll be using (in case of asic)
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