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issue about combinational loop in circuit.

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quan228228

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combinational loop

I am a junior IC design enigneer.
I read a "Clock Dividers Made Easy", SNUG Boston,2002 and found some issue which i dont understand. Could you help me?

The problme is below:
I really understand the logic function of clock divider by 3. But there is combinatinal loop in the circuit.
I knew we generally avoid combinational loop in circuit. So, Could you explain,
1. Could divider 3 work stable ? If yes, why?
2. how to judge that the combinational loop work well. For ex., there is setup and hold time requirments for sequential circuit.

Thanks!

attached is the paper i mentioned.
 

think about it, you will find it's a latch.

in fact, many sequential library cell is maked up by combinational feed back structure, you will find them in textbook or in custom layout.
 

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    quan228228

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Any othher issues are welcome.

Thanks!
 

archillios said:
think about it, you will find it's a latch.
Click to expand...

could you explain detail? i dont understand why it's a latch. Is it a D latch or other?

Thanks!

quan228228
 

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