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clock period constraint in ise9.1

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shahzad ahmad

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plz tell how can i learn to lay down clock period constraint
 

You set the clock period constraint in the UCF file below is a direct copy from one of my UCF files running under ISE9.1 The UCF portion is bracketed by #####s. This FPGA has numerous internal clocks running at the same frequency but different phases. They are each first assigned to a common group "dutclk". Then the TIMESPEC constraint defines the timing constraints that will be applied to all these clocks. With this constraint, the Xilinx tool can time all sychron. logic using those clocks. It will either make timing, or you will get error messages telling you where the problem areas are.
From the below example, you can look up the remaining details that you might need in the Constraints Guide that is in the help files.

###########################
NET "dqr_clk" TNM_NET = "dutclk";
NET "dqsr_clk" TNM_NET = "dutclk";
NET "dqw_clk" TNM_NET = "dutclk";
NET "dqsw_clk" TNM_NET = "dutclk";
TIMESPEC "TS02" = PERIOD "dutclk" 2.4 ns HIGH 50 %; # 433 Mhz
###########################

Here
 
See the "PERIOD" item in your ISE "Constraints Guide". It shows several ways to apply the constraint to your project. Banjo demonstrated the UCF method. Here's a simple Verilog counter project with a clock PERIOD constraint that's recognized by XST.
Code: 
module top (clk, count);
  input               clk;    // synthesis attribute PERIOD clk "50 MHz";
  output reg    [7:0] count=0;

  always @ (posedge clk)
    count <= count + 1;
endmodule
 
Yes you can embed these constraints within your Verilog codeas as Echo47 has described. The method works and is the one Xilinx often tries to push. However, this method has a large gotcha. Notice that the constraint is embedded within a comment! More than once, either myself or a co-worker have modified some code and editted or removed some comments only to find that it no longer mades timing. The reason is we mistakenly removed a synthesis attribute.
Strictly speaking, comments are NOT supposed to contain anything required by the code or the system. Making comments "functional" pieces of code goes against their very purpose. If you use this method, consider placing large warning messages around these attributes to warn others reading your code. I have the battle scars to demonstrate what happens when you don't.
 

I haven't made that mistake (yet!)

Yes, the "// synthesis attribute" method is bizarre and non-portable. I use it because I prefer keeping my entire design in one file, whenever possible.

How do you feel about using official Verilog 2001 attributes? (See section 3.8 of IEEE Std 1364-2005.) I use them sometimes, even though I think they look ugly, messing up my indenting. Xilinx ISE supports them. Example:
Code: 
module top (clk, count);
  (* PERIOD="50 MHz" *) input clk;
  output reg [7:0] count=0;

  always @ (posedge clk)
    count <= count + 1;
endmodule
You can combine multiple Verilog 2001 attributes:
Code: 
  (* PERIOD="50 MHz",LOC="C5" *) input clk;
The "// synthesis attribute" method would require multiple lines.

Verilog 2001 attributes also work inside a "generate" loop. I've run into troubles doing that in the UCF.
 

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