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How to calculate the gate count for a design in Design Compiler?

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sree205

sree205

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Hi,
could someone tell me how to calculate the gate count for a design in Design Compiler?

thanks.
 

design compiler + report_area

ok,that depend on the vendor,for example IBM
the gate counter =cell/3
 

design compiler report_area unit

Use the following command:

report_area

It generally gives the value as defined in the liberty file given by the standard cell library vendor.
Typical units are gate count, square micron,transistor equivalent.
 

report_area unit

deh_fuhrer said:
Use the following command:

report_area

.
Click to expand...
note down the area from the report and divide it by the unit cell area.
say u r using 90nm library find the area of a single nand gate in the datasheet and divide the area by this value u get the approx no of gates
 

report_area -hierarchy

1)Find the area of NAND2 in your lib, i.e. NAND2=10
2)Report_area of your current design, i.e. area=10,000
3)So your gate count in NAND2 is: 10,000/10=1000
 

understanding design compiler area reports

won;t sizeof_collection [ get_cells -hier * ] tell you the gate count after synthesis ?
 

cell area report units

rjainv said:
won;t sizeof_collection [ get_cells -hier * ] tell you the gate count after synthesis ?
Click to expand...
This command gives you how many "cells" existed in your design. Not gate count since one cell may be much larger than a NAND2 gate.
 

synopsys report_area units

The only accurate way of finding "exact" gate count is to run LVS on your design. It will report the exact number of gate structures.
 

command used to report cell counts in dc compiler

If you want to know the gate count for each cell from the library use the following command:
report_reference

It gives the list of the cells used in the present design, their area and count..
 

report_reference -s

Hello,
open the .lib file u are using for synthesis, find out the area of the smallest NAND cell. Divide the area obtained from report_area command ith this nymber, you will get gate count.
Sumit
 

report_ area units

what is the need of counting gates in FRONT end?

after doing backend flow .. v will be knwing FINAL gate count of Design
 

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