Need freq compen and LDO design master's help

Hi ,everyone :
I have one question :
The upload shcematic is a LDO . It uses the Miller compensation
as the upload paper using current buffer(T1 and C4) ?
In the shcematic uploaded , all cap is several pF , except the Cl ,which is
at least 2uF ( the datasheet specify " For stability , it must be at least 2uF) .
My question is :
1. The compensation looks like the paper's . When the load is low or output
current high , the Miller pole is dominant pole , and the output pole is
pushed to the high frequency . But when in quenscient state or low output
current state , the output pole is dominant pole . So what is the conversion
condition ? What is wrong with my analysis ?
2. Is there any zeros in the schematics to countact the poles ? As u can
see , there are too many poles .
3. What is the functions of the caps , what is the analytic equations
of the poles and zeros ?

hello,

With 2 uF( quite large ) output capacitor, I think your dominant pole will be in output (Vo) anyhow no matter what is the load condition.

The compensation scheme you showed is cascode compensation, aspired by Ahjua more than 20 year ago. It kills the feedford path while keep the feedback, so the miller effect remains.

Very glad to discuss with you on this .

can you explain more about your bipolar stage, I am bit confused !!

regards,

Thanks , Taofeng !
But ...but ....
I must say ....
If you are right ------ the output pole is the dominant pole ,for example,
Po = -100HZ .
For the second dominant pole , the Miller pole , let's say , Pm = -1000HZ.
At the frequency Pm, the output cap ,as you say , is too pig , So the output
node is ac groud almost , so the equivalent Miler cap , A2*Cc , almost 0 .
I mean , as you said , the output cap is too pig , so the Ahujia compensation
has no influence on the ac response of the circuit ( In fact , if the output pole
is the dominant pole . the Ahujia pole is at a very high frequncy ) . The simulation
show the same as my words !
Think it more ,pls .
But thanks for your response ,because you are the first one to response .

It is a commercial LDO product circuit . It really worth your time to analysis it !

fanrong,
This is my understaind of the ckt so far. Analyzing it open loop,

1. Output pole postion: not rocket science- Cb || Req where
Req = RL ||( (Rf+Rf1) || ro, MPass)
2. pole caused by C4 and T1 (as you have said) is from the paper.
3. Pole caused by C3 and T1 is also as said in the paper.
4. Zero caused by C3, R2 and T1, which is lower in freq than if R2 were not present. from the point of view of the C3, R2 is in series with the resistance 1/gm,T1. And, I think the zero position would be at (gm,T1 + R2)/C3
Since there is a capacitance that couples the bases of Q3 and Q4, and if capacitance C5 > C3, I'd say the poles at the bases of Q3 and Q4 which are already at a higher frequency are pushed out even further.
5. Pole is caused due to miller multiplication of C1 around T4. Thefore pole is 1/(A.C1.Ro1) where Ro1 is nodal impedance seen at drain of T1.
6. Zero is caused by R1 and C1.


Overall, it seems that the poles occuring at the gates of T4 and and drain of T1 is being pushed to lower frequencies.
The pole at drain of T1 is being pushed to much lower frequencies w.r.t output because of C4 and C3. Therefore, since it tracks with the output pole, i'd say this is probably the dominant pole.

And, zero in (6) above, is used to probably cancel the one at gate of T4. That leaves with one zero in (4) and one pole at the base of Q3 and Q4, which probably get cancelled with each other. If that is true, you are left with the output pole and the pole at drian of T1 which move relative to each other and hence a two pole system. It quite hard to make these statements without actually knowing the size of the caps.

Let me know if this helps.

These are my observations:

1. R1, C1 to compensate the zero due to mirror T3-T4.
2. C4 creates pole as in the paper.
3. C3 compensates the zero due to T2 (it is almost like a capacitor from gate of T2 to drain of T1).

I am not sure about C5, and the role of T5 and T6 (some startup ?)

Bupesh

hi
could you let us know which commercial product is this?

This is likely a simplified diagram, normally found towards the end of datasheets.