How to verify a decimation filter? (Emergency)

pdm decimation filter

I design a decimation filter(in verilog) for a 1-bit oversampled sigma-delta ADC.
But I don't have any idea to verify it.
Could anyone give me a hand?

Thanks a lot!

1-bit decimation filter

use fdatool in matlab to design ur filter quantize it to the required data format and generate a verilog/VHDL code + test bench. it would be really simpler to verify.

regards
srinivas

testing decimation filter

fdatool is easy to use, CIC filter and halfband filter can be realized
and quantized to fixed point resoulutons ,wish it help you!

4bit decimation filter

rsrinivas said:

use fdatool in matlab to design ur filter quantize it to the required data format and generate a verilog/VHDL code + test bench. it would be really simpler to verify.

regards
srinivas

Click to expand...

The decimation filter is a multistage filter.
Because I design each stage separately.
How the testbench of the decimation filter be generated in this case?

i do not how matlab does it internally.
but it may be something like this.
u have say three stages and each is an LPF.
so when u give an input to the first stage u know it's response which u may feed it to the second and so on and the resulting final result of the last stage may be put in an array in ur verilog or vhdl code and verified.hope i am clear.
this is a matlab generated sample code(not full)

module filter2_tb;

// Parameters
parameter clk_high = 5;
parameter clk_low = 5;
parameter clk_period = 10;
parameter clk_hold = 2;

// Nets
reg clk;
reg clk_enable;
reg reset;
reg signed [15] filter_in;
wire signed [15] filter_out;

integer n; //loop variable


reg signed [15] filter_in_force [0];
reg signed [15] filter_out_expected [0];

// Component Instances
filter2 u_filter2
(
.clk(clk),
.clk_enable(clk_enable),
.reset(reset),
.filter_in(filter_in),
.filter_out(filter_out)
);

initial
begin
// Constants
filter_in_force [0] <= 16'h7fff;
filter_in_force [1] <= 16'h7fff;
filter_in_force [2] <= 16'h7fff;
.
.
.
.
filter_out_expected [0] <= 16'h0000;
filter_out_expected [1] <= 16'h0000;
filter_out_expected [2] <= 16'h0000;
filter_out_expected [3] <= 16'h0000;
.
.
.
end
// Block Statements
always // clk generation
begin : clk_gen
clk <= 1'b 1;
# clk_high;
clk <= 1'b 0;
# clk_low;
end //clk_gen;

initial // reset block
begin : reset_gen
clk_enable <= 1'b1;
reset <= 1'b 1;
# (clk_period*2 + clk_hold);
reset <= 1'b 0;
end //reset_gen;

initial //The main block
begin
# clk_period;
filter_in <= filter_in_force[0];
# (clk_period*2 + clk_hold);
filter_in <= filter_in_force[1];
# clk_period;
for (n = 0; n<= 4970; n = n + 1)
begin
if (filter_out !== filter_out_expected[n])
$display("ERROR in filter test at time %t : Expected '%h' Actual '%h'", $time, filter_out_expected[n], filter_out);
if (n + 2 <= 4970)
filter_in <= filter_in_force[n + 2];
# (clk_period);
end
$display( "**** Test Complete. ****" );
$stop;

end //filter_in_gen;

endmodule


.

Added after 37 seconds:

this isnot forthe decimator it's for a bpf butterworth

Thank you gusy for the help.
The decimation filter use decimated by 16 and decimated by 4 to perform decimated by 64.
Matlab can generate stimulus for each stage.
But what I want to test is the result of decimated by 64.

By the way, if the ADC output is a 1bit data, does it mean the decimation filter has to be 1-bit input? Is it the sam if I queue the data to 4-bit and use 4-bit input decimation filter?

corgan said:

By the way, if the ADC output is a 1bit data, does it mean the decimation filter has to be 1-bit input? Is it the sam if I queue the data to 4-bit and use 4-bit input decimation filter?

Click to expand...

ur filter input is going to be constant say 16 bit inputs. what ADC r u using ? how is it 1 bit output?
why not use a 16 bit ADC so that there won't be any interface problem?

rsrinivas said:

corgan said:

By the way, if the ADC output is a 1bit data, does it mean the decimation filter has to be 1-bit input? Is it the sam if I queue the data to 4-bit and use 4-bit input decimation filter?

Click to expand...

ur filter input is going to be constant say 16 bit inputs. what ADC r u using ? how is it 1 bit output?
why not use a 16 bit ADC so that there won't be any interface problem?

Click to expand...

The ADC is a sigma-delta modulator with 1bit oversampled PDM output.