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How to use Verilog/VHDL codes for EDk tool

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nandhika

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hi,


did any one worked on EDk tool.........
using verilog or vhdl code hw to use EDK tool


thanks in advance
 

Re: doubt in EDk tool

The xilinx EDK enviroment is quite complex ...It can't be described simply .For one reason is always changing ..
You should refer to the development Flow to understand how to use it .But because is based a lot on Gnu .Is also a good idea to learn how gnu/unix development works
i mean gcc gdb ,make and some script languages or shells
 

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