create an Edif file from schematic

xilinx edif

Hi All,

does anyone know how to create an edif file from schematic. XST give an ngc file and I need to use an edif file.

Thanks

edif file

Hi,
Xilinx has a command line tool for this. It can be found in your Xilinx/bin/nt folder. The tool's name is "ngc2edif.exe" I don't know if ISE GUI has a way to call this tool or not. However, you can run it from the command line. While I have not used it recently, I used to use it all the time when we did schematics in Viewdraw and then used the Xilinx stuff for place and route.

edif xilinx

I used the ngc2edif. When I used the obtained edif file in ISE i get this error:

The EDIF netlist '*.edn' was created by the Xilinx
NGC2EDIF program and is not a valid input netlist. Note that this EDIF
netlist is intended for communicating timing information to third-party
synthesis tools. Specifically, no user modifications to the contents of this
file will effect the final implementation of the design.

create ngc edif

What exactly are you trying to do? Some simulators are require EDIF netlists which is the purpose of the tool. Since the Xilinx tool created the ngc file, there is no need to convert it to use it within the Xilinx tool.
If you want a sythesizable file, then I think you have to run the design through the "Translate" stage. This should give you an ngd file. The the tool is "ngd2edif.exe" Looking at my ISE9.1 install, they are no longer providing this tool. You would have to contact Xilinx to get a copy. According to their website, this tool was only supported up through Virtex2.

create edif xilinx

I am using Handel-C with DK. I need to design a core using Schematic and use this core with my handel-C code. In order to use it with Handel-C, I need an edif file. the two edif files (the one from the schematic and the one from my Handel-C) will be used during the P&R stage to generate the final bit file.

For example, I used a core from the Xilinx CoreGen. I combined the edif file from corgen it with the edif file from my Handel-C and it works. I was able to get the final bit file.

Added after 3 minutes:

can I convert my schematic to VHDL in ISE?

how to generate ngc file

You can convert to VHDL with a command line tool. It is "ngd2vhdl.exe". (Bet you could have guess that!) While the purpose is to be used in simulation, it may work also for Place and Route. The reason is, it uses the translated output file and not the sythesized file. Therefore, it should know about the architecture of your chosen FPGA.

I used to have to do something similar several years ago. The Xilinx tools at that time had FPGA_Express as part of the tool chain. What I would do was optimize with FPGA_Express using a "do not insert IO pad option". The I could choose an export netlist option and save it as an EDIF.

Did you search the Xilinx support site?

www.support.xilinx.com

This should have been asked before, there is probably an APP note on this.

Added after 6 minutes:

Here is another idea:
Turn both your existing EDIF and your NGC into two symbols. The call these symbols from a higher level schematic or HDL code that is just an interconnect wrapper. In this way you can merge the two entities into one project. As long as the interface does not change, you can also quickly change either portion. Please see :

**broken link removed**

xilinx regenerate top.vhf

Bashma said:

can I convert my schematic to VHDL in ISE?

Click to expand...

If you are using the latest versions of ISE, you may already be getting schematics converted to Verilog or VHDL. The generated files are .vf for verilog files and .vhf for VHDL. Select the design flow for VHDL to convert schematics.

The result will be structural code using the Xilinx primitive components. Each macro component will generate one design entity per file, as needed - the design entities are not shared across multiple files.