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Help me implement RSA encryption algorithm on FPGA

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onteri

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some help

hi guys i am trying to implement RSA encryption algo on FPGA. my idea is to first generate random numbers and then check them for being prime numbers or not...
i am using linear feedback shift registers for random number generation. but now i am stuck in primality testing.....can anyone help me on this!!!please
 

some help

look out for euclid's algorithm in wikipedia. it gives a lot of info on primality checking.
 

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