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Can I simulate Verilog and C code simultaneously ??

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vsrpkumar

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query in simulation

I designed a first order IIR filter in verilog with floating point coefficients.I am writing equivalent C code.What my doubt is is it possible to simulate both verilog and C code simultaneously with the test vectors defined in verilog test bench.I think there will be solution for this case.I am using ncverilog compiler and gcc compiler
 

Re: query in simulation

I think you can. Instead of directly writing test vectors inside verilog testbench , write them in .txt file. Then you can read those .txt files by verilog file I/O functions which becomes standard in verilog 2001. The C model should also read those .txt file by file i/o operations in C and perform IIR algorithm. Lots of company in industry doing this. Even now sequential equivalence checking is possible between C algorithm and HDL by Calypto's SLEC tool and Industry is using it.
 

Re: query in simulation

vsrpkumar said:
I designed a first order IIR filter in verilog with floating point coefficients.I am writing equivalent C code.What my doubt is is it possible to simulate both verilog and C code simultaneously with the test vectors defined in verilog test bench.I think there will be solution for this case.I am using ncverilog compiler and gcc compiler
Click to expand...

Yes you can, look for PLI in ncverilog documentation.

Regards
Ajeetha, CVC
www.noveldv.com
 

query in simulation

Please use PLI/VPI/DPI with all your buffers as pointers passed through interface. You can very well do that. Best way is to use a systemc Testbench.
Sumit
 

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