nguyentl
Newbie level 6
Hi friends,
I currently verify the whole DRAM circuit using verilog. For analog circuits, I have to write models for them in abstract level. I now verify only functionality not timing. The delay of all components are predefined and not precise. I am thinking to use SDF or SPEF files for better performance but I do not have any experience. Could you tell me how I can generate these files and how to use them in the simulation. We only design DRAM in transistor and layout levels. In some part we use standard cells. And we use cadence to design and run simulation.
Thanks for help.
Regards,
TLN
I currently verify the whole DRAM circuit using verilog. For analog circuits, I have to write models for them in abstract level. I now verify only functionality not timing. The delay of all components are predefined and not precise. I am thinking to use SDF or SPEF files for better performance but I do not have any experience. Could you tell me how I can generate these files and how to use them in the simulation. We only design DRAM in transistor and layout levels. In some part we use standard cells. And we use cadence to design and run simulation.
Thanks for help.
Regards,
TLN