ethan
Member level 3
Hi there,
I got a bunch of warnings when i compile my controller, a finite state machine written in VHDL. Here are the warnings I got:
Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "partition1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "partition1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "signed1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "signed1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
And many same warnings with different signal names.
Warning: Latch sad_op$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal state.sad_1
What is Port D and ENA? Are they the input D and Enable for the state register? I do not have them in my code.
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "sad_op$latch" is a latch
Warning: Node "mult32_op$latch" is a latch
......
Can anyone give me a glue why I got all of these warnings? My state machine has three processes:
1. the state transistion process. The next state becomes the current state at rising clock edge.
2. the output signal process: at every state, some signals that depend only on the current state are descibed directly using the assign statement "signal <= '1' ", for example, others that depend both on the current state and the input signals are described using "if" statement.
3. the next_state process: next state depends on both current states and the input signal. At every sate, next state is described using "if" statement as for output signal that depend on both input and current state.
Also, although my code went through compilation, I got this error message when simulating it:
Internal Error: Sub-system: SIM, File: sim_preprocessor.cpp, Line: 2777
Illegal state bit setting!
Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version
Thanks for helping me out! Any ideas are welcome!
I got a bunch of warnings when i compile my controller, a finite state machine written in VHDL. Here are the warnings I got:
Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "partition1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "partition1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "signed1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "signed1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
And many same warnings with different signal names.
Warning: Latch sad_op$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal state.sad_1
What is Port D and ENA? Are they the input D and Enable for the state register? I do not have them in my code.
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "sad_op$latch" is a latch
Warning: Node "mult32_op$latch" is a latch
......
Can anyone give me a glue why I got all of these warnings? My state machine has three processes:
1. the state transistion process. The next state becomes the current state at rising clock edge.
2. the output signal process: at every state, some signals that depend only on the current state are descibed directly using the assign statement "signal <= '1' ", for example, others that depend both on the current state and the input signals are described using "if" statement.
3. the next_state process: next state depends on both current states and the input signal. At every sate, next state is described using "if" statement as for output signal that depend on both input and current state.
Also, although my code went through compilation, I got this error message when simulating it:
Internal Error: Sub-system: SIM, File: sim_preprocessor.cpp, Line: 2777
Illegal state bit setting!
Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version
Thanks for helping me out! Any ideas are welcome!