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A super fast random number generator

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hav to design a 4-bit random number generator, to be
used for test pattern generation. The random number generator uses the Linear
Feedback Shift Register approach.the figure has been attached..

**Have to achieve high speed operation and nothing else.

**Area and power are not an issue in this design problem

wat is the max possible speed i can achieve (ie.,hav to minimize the clock speed to maximal extent)

i have to design this n have to do the layout part also in cadence
plzzzz help out
 

I think you've to design the registers and gates the fastest implementation you can .Fast logic families as CML (Current Mode logic) ,ECL(Emitter Coupled logic) or LVDS (Low Voltage Differential Signaling ) can be used .You can also try placing positive skew at long paths to increase clock speed but you have to be careful in oder not to have race at your circuit .
The fastest clock speed depends on the technology you use, but some fast dividers can work at the GHz range so I believe that you can get a fast circuit .
 

cud u plzz elaborate how to implement n something regarding skew.. i dint understand sorry for asking again
thnx
 

Sorry for the late reply .Regarding the CML, the following link is for an IEEE paper regarding a divider operating at 10 GHz .I think you can use the same flip-flops as those used at this paper .

http://www.ece.uci.edu/~payam/FF_Divider_ISCAS04.pdf

Regarding +ve skew, on increasing +ve skew at certain path, delay of this path will decrease by the value of this skew but you may risk having race and I'm not sure if this idea may help you .You can check Rabaey's book "digital integrated circuits"2nd edition chapter 10 pages 495 to 500

Once again I'm sorry for the late reply .
 

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