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the buffer in the low dropout regulator

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xxf_86

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Hello all, now I start to design a low quiescent current, low dropout voltage regulation with CMOS processor, could you please tell me some structure of the buffer in ldo, the spec is wide bandwith, low quiescent and enough slew rate.
 

source follower for example.
sometimes merely buffer could not resolve the problem of stability, since the parasitic capacitance of the gate of the buffer forms anther non dominant pole with pre-stage, which may easily within unity bandwidth of LDO loop.
 

What is the reference voltage available?What is the min. load cap. available?
What is the required PSRR worst case?How much quiescent current is available and is dynamic biasing option available?


A possible architecture for your specs could be:

PMOS Diff Amp, followed by a common source NMOS stage with resistive load followed by the pass transistor and the feedback resistor divider.This architecture will have low quiescent current loop gain and thus PSRR.
 

How can you do a LDO with source follower ???? To get a very low drop out you must have a PMOS at the output. Everybody saying that a NMOS could be use don't have LDO problem or had Native NMOS device.
 

NMOS pass transistor is possible to be used for getting LDO voltage only if you boost the supply voltage and drive the OTA with it and thus can have a high enough gate voltage to drive the NMOS pass transistor.
 

can anyone explain why add a buffer can improve PSRR , thanks in advance
 

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