plz friends help me with the coding for PWM for Spartan 3E

friends
i need the coding to generate a PWM waveform from the Spartan 3E stater kit to a MOSFET on a circuit via a gate drive. the waveform can be at logic 0 or 1.
eagerly waiting for your reply
thanks

Re: plz friends help me with the coding for PWM for Spartan

Attached is pwm circuit

Re: plz friends help me with the coding for PWM for Spartan

here is the code, just give the value for clock_divide_reg_init ,duty_cycle_reg_init

and enjoy prototyping

---------------------------------------------------------------------------------------------

module pwm
(
clk,
pwm_enable,
resetn,
pwm_out
);

parameter clock_divide_reg_init = 32'h0000_0000;
parameter duty_cycle_reg_init = 32'h0000_0000;

//Inputs
input clk; //Input Clock to be divided
input pwm_enable; //Enable signal
input resetn; //Reset

//Outputs
output pwm_out; //PWM output

//Signal Declarations
reg [31:0] counter; //PWM Internal Counter
reg pwm_out; //PWM output

reg [31:0] clock_divide_register; //Clock divider register
reg [31:0] duty_cycle_register; //Duty Cycle vale register

//Start Main Code
always @(posedge clk or negedge resetn) //PWM Counter Process
begin
if (~resetn)begin
counter <= 0;
clock_divide_register <= clock_divide_reg_init;
duty_cycle_register <= duty_cycle_reg_init;
end
else if(pwm_enable)begin
if (counter >= clock_divide_register )begin
counter <= 0;

end
else begin
counter <= counter + 1;
end
end
else begin
counter <= counter;
end
end

always @(posedge clk or negedge resetn) //PWM Comparitor
begin
if (~resetn)begin
pwm_out <= 0;
end
else if(pwm_enable)begin
if (counter >= duty_cycle_register)begin
pwm_out <= 1'b1;
end
else begin
if (counter == 0)
pwm_out <= 0;
else
pwm_out <= pwm_out;
end
end
else begin
pwm_out <= 1'b0;
end
end


endmodule


---------------------------------------------------------------------------------------------

Re: plz friends help me with the coding for PWM for Spartan

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity PWM is
port ( reset : in std_logic;
clk : in std_logic;
period : in std_logic_vector (13 downto 0); -- unsigned
width : in std_logic_vector (13 downto 0); -- unsigned
dout : out std_logic);
end PWM;

architecture rtl of PWM is

constant n_bits : integer := 14;

signal period_counter : std_logic_vector (period'range);
signal width_counter : std_logic_vector (period'range);
signal last : std_logic;
signal last_d : std_logic;
signal width_flag : std_logic;
constant zeros : std_logic_vector (n_bits-2 downto 0) := (others=>'0');

begin

-- The period counter
process (reset, clk)
begin
if reset = RESET_ACTIVE then period_counter <= (others=>'1');
elsif clk'event and clk='1' then
if last='1' then period_counter <= period;
else period_counter <= period_counter - 1; end if;
end if;
end process;


-- The last cycle flag. Active on the last cycle of the period
process (reset, clk)
begin
if reset = RESET_ACTIVE then last <= '0'; last_d <= '0';
elsif clk'event and clk='1' then last_d <= last;
if period_counter = (zeros & "1") then last <= '1';
else last <= '0'; end if;
end if;
end process;


-- The width coutner
process (reset, clk)
begin
if reset = RESET_ACTIVE then width_counter <= (others=>'0'); width_flag <= '0';
elsif clk'event and clk='1' then
if width_counter = (zeros & "0") then width_flag <= '1';
else width_flag <= '0';end if;
if last='1' then width_counter <= width;
else width_counter <= width_counter-1;end if;
end if;
end process;

-- The output
process (reset, clk)
begin
if reset = RESET_ACTIVE then dout <= '0';
elsif clk'event and clk='1' then
if last='1' then dout <= '1';
elsif width_flag='1' then dout <= '0'; end if;
end if;
end process;

end rtl;