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What is logic optimization and what are the methods for it?

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logic optimization

hi,

can anyone tell wat is logic optimization?? & give some methods??

also y we use higher metal layer for VDD & VSS its 'coz of lower restivity as the metal layer increases its resistivity decreases.......correct me if i'm wrong.....
i want in detail.........

thanks
 

Re: logic optimization

Hi,
You would optimize logic to meet specific constraints - i.e. timing or area. For example where you have a design where a gate has a high fanout and is struggling to meet timing you may clone it so that each gate drives a lower load and can therefore timing is faster, obviously this is a trade off as you are increasing the area.

You generally use the high thick metal layers for power because of their thickness they are much lower resistivity and you get much lower IR drop across your power mesh - in turn this reduces the effects of on chip variation.

Hope that helps
 

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