UART (1v8 and 2v8) interface to Xilinx Spartan3 - help need

Hello,

I have one module that has two operating UART, UART1 is 2V8, and 3V tolerant. UART2 is 1V8. I want to interface these UART to a Spartan3 FPGA, which i believe I/O signals are [0..+3.3V].

Do i need a transceiver to switch levels? Could you recommend me one reference?

Thanks

Take a look at the Fairchild parts such as FXLP34. These devices have two power pins and can translate between lots of different voltage levels.

The one thing to watch out for is whether the UART expects the transmission channel to invert the signal. For example, the RS232 interface IC contain logic inverters. Therefore if the standard is to invert the signal, you must include this inversion in your translator selection.

The Spartan FPGA has logic divided into banks. Each bank can have a different I/O power source and a different I/O standard. If your PCB is not fabricated yet and you have lots of freedom assigning pins, you could bring one UART into a 3.0V bank and the other UART into a 1.8V bank. Then even if the channel requires inversion, you could integrate these inverters into the FPGA and not require level shifting at all.

If your PCB is already done, or you do not have control over which pins will be used for interfacing then level shifting or translator chips will be required.

Re: UART (1v8 and 2v8) interface to Xilinx Spartan3 - help n

Hello banjo,

Thanks for your help. I took a look to the Spartan-3 manual... and i believe you are talking about VREF pins. Manual states:


And with Table 7: Single-Ended I/O Standards (Values in Volts) and Table 8: Differential I/O Standards help i understand what you are saying.

Too bad that i have already routed and fabricated my PCB. I'll point this for a revision .

I guess i have to add an extra IC.

Thanks again

Re: UART (1v8 and 2v8) interface to Xilinx Spartan3 - help n

It is possible that simple serial resistor on higher voltage trasmiter will be all what you need. If the length of the connection and transmision speed are not very high.

bis

Hi,

VREF is only part of the issue. Interface standards that use differential inputs use the VREF voltage to set the switching level. Single-ended standards do not use the VREF and you can actually use these pins as additional I/O.
Along with the VREF, you have to properly set up the VCCO for each bank. For example, if you want to run SSTL1.8 on a bank this is a differential I/O standard with 1.8V VCC and 0.9V VREF. You have to get both of these to get it to work.

From the Xilinx datasheet, you can determine the VREF and VCCO requirements of each interface standard. Some interface standards can be mixed within the same bank because their VREF and VCCO requirements do not conflict. For example LVCMOS2.5 and SSTL2.5.

Again, since your board is already done, you probably will need a translator for the current revision.