jfyan
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hi all,
i want to know what will happen to PLL's performance when input reference clock is high about 100-500MHz.
for example, as i observed, when the input clock is about 200MHz, the static phase error is very small, less than 10ps. and some other the bad effects such as leakage currents, mismatch in charge pump currents, can be smaller compared with low input clock, right?
what else i want to discuss is dead zone, i find it is a very big problem, and i think because of dead zone, the control voltage to the vco is random walking when the loop is in "locking". i don't know whether above are right? so let's have a hot talk.
good luck
jeff
i want to know what will happen to PLL's performance when input reference clock is high about 100-500MHz.
for example, as i observed, when the input clock is about 200MHz, the static phase error is very small, less than 10ps. and some other the bad effects such as leakage currents, mismatch in charge pump currents, can be smaller compared with low input clock, right?
what else i want to discuss is dead zone, i find it is a very big problem, and i think because of dead zone, the control voltage to the vco is random walking when the loop is in "locking". i don't know whether above are right? so let's have a hot talk.
good luck
jeff