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A question for mixed Language RTL coding

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windowX

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hi, all
I am RTL coding with mixed language and I am confused by
a problem. when writing a Verilog HDL program, I want to instant
a component defined in VHDL, but in the VHDL, there is some "generic",
how can I pass the value to these "geneic" in Verilog.

Plz help me, thanks very much.
 

windowX said:
hi, all
I am RTL coding with mixed language and I am confused by
a problem. when writing a Verilog HDL program, I want to instant
a component defined in VHDL, but in the VHDL, there is some "generic",
how can I pass the value to these "geneic" in Verilog.

Plz help me, thanks very much.
Click to expand...

Use Verilog parameters for the same. Since your post asked for simple instantion use model, a sample code is:

Code: 
module my_vlog_top;

parameter VLOG_Param_1=10;
parameter VLOG_Param_2=1;


  vhdl_dut #(.VHDL_Generic_1(VLOG_Param_1), 
                  .VHDL_Generic_2(VLOG_Param_2) ) 
     dut_0 (<ports>);

Good Luck
Ajeetha, CVC
www.noveldv.com
 

Thanks so much, and I will try it now.

btw:your website seem wonderfull...
 

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