Help on ESD failure analysis

hi,
I have an ESD issue I can not explain. Hope to get you ESD gurus's help.

Pls. see the attached diagram. This is the connection for the failed pin. The Pin did not pass the HBM 1500V for IO to IO- ESD ZAP. I can not understand why.

First, I doubt the gate is damaged. But the other pins which only connected the gate with same ESD protection is OK.It shows the ESD diode works well. So I doubt the NWELL resistor and the NMOS Tr whith its drain tied to the NMELL resistor maybe the criminal.

But I can not think out what possible failure mechanisim exsist.

BTW, it is the 0.5um CMOS process. The ESD diode can stand the 4000V ESD ZAP.

Would you help me on it?

Thanks a lot
Dandelion

Is the ESD diode not big enough?

Hi Chang,
ESD is a very complex issue, and there may be tons of things that can go wrong, and it may very well be a layout issue. From the schematic, the points I can say are:

1. Your gate to the Diff pair NMOS is directly connected to the PAD, the gate might get damaged easily if the ESD diodes don't have low enough resistance path to shunt the ESD current through to the main clamp. Is this I/O very far from the main clamp?
2. If the other transistor (whose drain is connected to nwell and then to pad) is getting damaged then maybe your Nwell resistor is not high enough.
3. Check your bus routing and calculate the total resistance seen by the ESD path that is failing. If its high then some node may be rising in voltage high enough to damage a device.

Hi Chang830,

For ESD zapping, there are several modes
(1) IO vs IO
(2) IO vs VDD
(3) IO vs VSS
(4) VDD vs VSS

All above use +/-ve ESD pulse.
Please state clearly your results and pls state clearly your whole chip pin assignemt so that we can analyze for you.