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Synthesis Tricks to reduce Congestion

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shahal

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synthesis tricks

If my design has a lot of congestion due to MUXes. What kind of synthesis tricks can I play to better guide DC into picking mux implementations that are better for congestion
 

The best mux implementation for conjestion is using a mux standard cell. Cant do much better than that, in terms of logic. You could "set_dont_use" on all cells smaller than a certain size, this will blow up your overall design size, giving more routing area, but you are better off just having a lower utilization block post-p&r.
 

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