abt useful clock skew

can any body have useful clock skew material or information .
plz upload the material as soon as possible.

Consider a design with 3 flip-flops, all clock inputs fed using the same clock signal. Now, the clock edge that FF2 sees may be delayed to that of FF1 and also that which FF3 sees can be delayed with respect to FF2.

This delay in the clock signal between two adjacent FFs (FF1 - FF2 or FF2- FF3) is called Clock Skew. This if the clock is skewed, the clock edges arrive at different times to the sequential logic. This may cause timing as well as metastability problems in sequential ckts.

There are 2 methods to minimize clock skew:

1. Delay the clock.
2. Delay the Data.

1. Delaying Clock
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We can delay the clock between adjacent FFs such that all the clock edges arrive at the same time. The drawback in this methos is that we may loose a few clock edges while synchronizing.

2. Delaying Data
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The second method is to delay the data arrival between the two FFs. Thus the clocks arrive delayed and the data is delayed and synched with these clock edges.

This pdf at this link may be useful regarding useful skew