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Problem with VHDL code for Spartan II

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msemse

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hi,
I have a problem with a SpartanII design. I am driving 5V logic devices with spartanII. These logic devices are L293D's for DC motor driving and AM26LS32 for receiving quadrature encoder signals. Spartan II's are 5V tolerable. I am working on a servo controller.
My problem is i am writing vhdl code. My first vhdl code does not involve all
the pins in the entity. When i write a new code and it includes additionally 1 pin and i write something to this pin my design fails. I could not understand the problem.
Has anybody got any idea to work around this problem?
--
sinan
 

Spartan II problem

What do you mean by, "my design fails"? The FPGA does not function as intended or the Xilinx tools fail to produce a bit file?

The Xilinx tools are optimizing your code. If you have lots of VHDL that does not have a valid IO pin as an input or does not ultimately drive an IO pin, the tools were remove this logic from the design. After you add the IO pin and recompile, the tools no longer strip out the logic and the design may no longer fit into the part.

Please provide info to exactly what stage of the build process fails and what error messages are given.

Are you storing servo settings in memory? Perhaps the design is running out of RAM blocks.
 

Re: Spartan II problem

Dear Banjo,
Thanks for your reply.
I am using XST and the ISE program can generate the bit file. No error messages occurs. When I have download the bit file to the FPGA, I am expecting that the system before will still work because the new added code does depends on the system before or the new code does not interacts with the old system but when
i add a new pin and make a assignment statement like
new_pin <= '1';
OR
new_pin <='0';
and assign a phsical pin in the ucf file like
NET new_pin LOC=p_something
the ISE program can generate the bit file but when i download it to fpga the old design fails.
Have you got any idea?
best regards
--
sinan
 

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