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How to balance inter_clock domain skew ?

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roy_ece

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inter_clock skew

hi,
how do we balance skew for inter clock domain.
thank you
 

why balance skew

Let me understand your question. Say you have two clock domains and you want to balance skew between them?

1) Use one clock domain?
2) Maybe use some sort of PLL circuit that will align your phase wrt other clock domain.
 

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