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Help on VHDL design of counter using LUT of FPGA

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mlalla

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code lut for fpga

Hi

I need help in devloping vhdl code for a up/down counter using LUT in virtex fpga..Using the Luts avaialble in a CLB i need to develop structural code such that it acts like a up/down counter...i have been able to construct an up counter but am unable to find a solution to include both of them! Please help me out i really am very much stuck
 

hi,
I am facing the similar problem. Please let me know if u find a solution for it
 

Implement this circuit..

**broken link removed**
 

Thanks for the reply vipin. But I need to use components in virtex4 fpga and build a up down counter. so I need to use a 16:1 mux and a D FF (D FF if needed). But in the link there are gates I need it with a 16:1 mux. So any help in this direction is really helpful.
 

Its not a 16:1 mux, its a 4 input LUT. You cant build a counter with mux, you need gates.
 

A 16:1 mux can represent all possible functions of a input LUT by placing a 16 bit constant at the mux inputs.

But I don't see a reasonable purpose for this method, because FPGA elements are LUT not mux.
 
FvM said:
A 16:1 mux can represent all possible functions of a input LUT by placing a 16 bit constant at the mux inputs.

But I don't see a reasonable purpose for this method, because FPGA elements are LUT not mux.
Click to expand...


Thanks for the replies. I had to build a pattern generator/updown counter using LUTs. I dont know how to do this because it has 4 inputs and one output and I need a 4 bit up down binary counter .so thats why am using LUT's 16:1 mux . Could you please let me know how to achieve it using constant inputs , or any other efficeint way to achieve this using LUTs.

- Pri
 
Last edited:

Is there a specific reason why you're using LUTs instead of a carry chain? Now I'll admit that for a 4 bit counter it doesn't matter so much, but for say a 16-bit counter it might make the difference between failure and success on meeting timing constraints.

I'd think that if you entered behavioral code for an up/down counter the tools would come up with a carry chain.
 
mrflibble said:
Is there a specific reason why you're using LUTs instead of a carry chain? Now I'll admit that for a 4 bit counter it doesn't matter so much, but for say a 16-bit counter it might make the difference between failure and success on meeting timing constraints.

I'd think that if you entered behavioral code for an up/down counter the tools would come up with a carry chain.
Click to expand...


I need to build a updown counter using a CLB in virtex -4 FPGA. I can only use components inside it
i.e. LUT. So I need to bulid a 4bit binary up down counter using LUTs
 

pgadde1 said:
I need to build a updown counter using a CLB in virtex -4 FPGA. I can only use components inside it ...
Click to expand...

Mmmmh, since when does a virtex-4 CLB not contain carry chains?
 

The exact problem specification still isn't clear. As already mentioned, the normal way is to define the counter operation in a hardware description language of your choice and let the synthesis tool implement it. You can inspect the gate level netlist to check how it fit's into LUTs and registers.

I assume, that you have been given a homework problem that prescribes a specific way how to implement the design. But seriously speaking, you can't expect that all FPGA practioneers at edaboard will forget their proven methods to implement a design for to follow an arbitrary and badly explained design idea.
 
Quick tip for lazy people: Do what FvM just said. :p

That being "As already mentioned, the normal way is to define the counter operation in a hardware description language of your choice and let the synthesis tool implement it. You can inspect the gate level netlist to check how it fit's into LUTs and registers."

Make a boring bit of verilog/vhdl "the usual way" and synthesize it. Then in the technology view you'll see that it uses LUTs (yay! conform homework spec!) and XORCY carry stuff. All happily in a virtex-4 CLB.

That should give you some inspiration. If you then decide that you STILL want LUTs more LUTs and only LUTs, you can implement the logic of the XORCYs etc in more LUTs. Either that or engage brain and think of something clever. ;)
 
mrflibble said:
Mmmmh, since when does a virtex-4 CLB not contain carry chains?
Click to expand...

I am not aware of this concept of using carry chains in a CLB and programming in vhdl. I 'll start looking in that direction. Thanks

- - - Updated - - -

Yeah I was given a project, asked me to develop a Test pattern gernerator(up down binarycounter ) which uses a CLB in FPGA in VHDL . So I tht I can use LUTs Because it has muxes so its easy to write the code using case statements. But after reading all this am thinking my design can be implemented in a btr way. Sp pls share with me any proven methods for this.
 

Well, quick example...

Code Verilog - [expand]
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reg [7:0] count;
wire direction;
 
always @(posedge clk) begin
    if (direction==1'b1)
        count <= count + 1'd1;
    else 
        count <= count - 1'd1;
end


That'll incorporate the concept of carry chains for you, without having to think too hard about it. XST will do al that for you. ;) It doesn't have to be any harder than the above.
 
mrflibble said:
Well, quick example...

Code Verilog - [expand]
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reg [7:0] count;
wire direction;
 
always @(posedge clk) begin
    if (direction==1'b1)
        count <= count + 1'd1;
    else 
        count <= count - 1'd1;
end


That'll incorporate the concept of carry chains for you, without having to think too hard about it. XST will do al that for you. ;) It doesn't have to be any harder than the above.
Click to expand...


Thankyou :)
 

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