Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

questions about buried via in Protel DXP

Status
Not open for further replies.
A

antenna_abc

Member level 3
Joined
Dec 22, 2005
Messages
58
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,835
Hi, everyone. I have some questions about drawing buried vias connecting two conducting plates on a 4-layer PCB by using Protel DXP.

My questions are:

1. How can I define the buried via connecting ground plane and intermediate copper layer with square conducting patches on it? Actually it seems that I cannot directly place the via/hole on the PCB in Protel DXP.

2. How do I define different shapes of conducting patch in Protel DXP?

Thanks in advance.
 

questions about buried via in P*otel DXP

For Buried & Blind via selection and connection to power plane you have to selected correct PCB Tamplets or create user defined board
You can use polygon/copper pour
 
Yes, you can directly place a via. You use either the menu command, Place>Via, or the shortcut keys 'PV'. After you enter the place via mode, you hit 'Tab' to bring up the properties menu that allows you to select the start and stop layers, as well as the hole and annulus size.

Vias in DXP can only have round annuli. If you want a square patch, you'll have to make it by using a fill on the appropriate layer.
 
Thanks for all your comments. However, I found that some Design Rule Check (DRCs) do not allow me to place the via directly. I am wondering which one is appled to control the via placement in the DRC in protel. Thanks once more~
 

It is most likely the 'Clearance' rule that is causing you problems. It is probably set up as 'All'>'All' meaning that nothing is allowed to be closer than the specified clearance to any other object.

You can either adjust the rule to allow vias as an exception, or you can go to Preferences>PCB Editor>Interactive Routing and change the action from avoid obstacles to ignore obstacles. The burden then is on you to make sure that you don't violate clearance rules - the automation will allow you to override the rule settings.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top