vhdl code needed??????/

vhdl code for piso register

Could any one provide me the code for serial in parallel out and parallel in serial out shift register in STRUCTURAL?
i did it in behavioural bt cud nt do it in structural!

4 bit sipo vhdl

what is structural ??

vhdl code for sipo

3 type of modelling:
Behavioral , dataflow and structural

i want it in sturctural .. thx!

component vhdl code

dear sir

i need serial to parallel input 1 bit stream and output 3 bit stream
BR
Amer

parllel in parllel out vhdl code

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:50:15 02/06/2007
-- Design Name:
-- Module Name: shift1_8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 8-bit load, 1-bit shift out (msb first)
--
-- if load is '1', a new value is loaded from d.
-- if shift_out is '1', next bit is shifted out (msb first).
--
entity shift1_16 is
port (Din: in std_logic;
clk: in std_logic;
reset: in std_logic;
Pout: out std_logic_vector(2 downto 0));
end entity;

architecture Behavioral of shift1_16 is
signal data: std_logic_vector(2 downto 0);
begin
process (clk, reset)
begin

if reset = '1' then
data <= "000" ;
elsif rising_edge(clk) then
data(0)<= data(1);
data(1)<= data(2);
data(2)<=Din;
pout<= data ;
end if;

end process;

Pout<= data ;


end Behavioral;


Anything else my bro???

hey i think this forum is boring .. no1 here to help ! i asked 3 times n cooked up myself later on! n here helping !! ppl do smthing!! by helpin each otha u dn lose nething!

clik on helped me [] enjoy!!

parallel in serial out vhdl

Hi
such simple programs would be better if u write on u r own by going thru the structures,iam giving code for sipo and piso in structural model using D-ff.

library ieee;
use ieee.std_logic_1164.all;
entity sin_pout is
port(cp:in std_logic;
si:in std_logic;
s0,s1,s2,s3:buffer std_logic);
end sin_pout;
architecture str in_pout is
component D_FF
port (CLK,D : in std_logic;
Q : out std_logic := '0';
NQ : out std_logic := '1' );
end component;
begin
a1_FF port map(cp,si,s0,open);
a2_FF port map(cp,s0,s1,open);
a3_FF port map(cp,s1,s2,open);
a4_FF port map(cp,s2,s3,open);
end str;


library ieee;
use ieee.std_logic_1164.all;
entity piso_d is
port(A,B,C,D,clk,shift:in std_logic;q1,q2,q3,q4:buffer std_logic);
end piso_d;
architecture piso of piso_d is
signal load:std_logic;
signal w1,w2,w3,w4,w5,w6,w7,w8,w9:std_logic;
component d_ff
port(d,clk:in std_logic;q,qbar:buffer std_logic);
end component;
component and2
port(a,b:std_logic;cut std_logic);
end component;
component or2
port(a,b:std_logic;cut std_logic);
end component;
begin
load<=not (shift);
ff1:d_ff port map(A,clk,q1,open);
g1:and2 port map(load,B,w1);
g2:and2 port map(load,C,w2);
g3:and2 port map(load,D,w3);
g4:and2 port map(shift,q1,w4);
ff2:d_ff port map(w7,clk,q2,open);
ff3:d_ff port map(w8,clk,q3,open);
g5:and2 port map(shift,q2,w5);
g6:and2 port map(shift,q3,w6);
g7r2 port map(w1,w4,w7);
g8r2 port map(w2,w5,w8);
g9r2 port map(w3,w6,w9);
ff4:d_ff port map(w9,clk,q4,open);
end piso;

vhdl code for sipo register

it appears that you can use the template in software

sipo vhdl code

thx a lot vinodh ! n i followed ur suggestion when it was in ur heart dear...i made it !! bt had a very lil time daz y posted such a stupid request .. hope u understand! neways thx a lot !