need u help on this current limiting analysis

Added after 22 minutes:



This is a LDO's driver and current limiter .
The refernce , pmos pass device , feedback resistor network are not shown here.

Vss is input voltage , Vss=6V
Vb1,Vb2 is the bias voltage , make the current of unit W/L current source and sink
0.5uA .
Vo is the LDO's output , Vo=5V
Vref is the refence , Vref=1.2V
Vfb is the feedback , Vfb=1.2
shut is the shut signal , Vshut = 6V
The W/L :
M1 : 32/3 , M2: 8/80 , M3 : 64/8, M4 : 32/8
M5 : 64/8 , M6 : 32/8 , M7 : 8/3 M8 : 8/80
M9 : 16/16 , M10 : 16/16 M11 : 16/16

The driver and current limiter should limit the current :
When Vo > 0.8 , and not in low drop out region , Imax=400mA
when Vo<0.8 , Imax=200mA
When low drop out , no current limit .
My question is :
As u can see, when Vo< 0.8V , M1 ,M 3 are shut off .The current source M 9, M 12 can't balance the curent of M 5, M7,M12 when vo <0.8 . So the voltage of
A is very low . So how the driver and current limiter limit the current under 200mA
when Vo < 0.8V .

Re: need u help on this current limit analysis

Still no one help me ?

need u help on this current limit analysis

Let me try

Added after 24 minutes:

When Vo<0.8, what is Vref and Vss?
What do A B C D connect to?

need u help on this current limit analysis

C is connected to the gate of the pass PMOS device .

Added after 1 minutes:

Vref is still 1.2v , and VSs 6 V when Vo <0.8V

Added after 36 minutes:

Would anyone give me any clues ?

need u help on this current limit analysis

There is no sense of current , how can you limit it ?

Re: need u help on this current limit analysis

The current limit is by monitoring the voltage of the gate of the pass device (the node of C as the picture shown) . It is not by current sense of resistor .

Any one has the experiece of this kind of current limiter ?

Still no one help me ?

Added after 4 hours 29 minutes:

C is connected to the gate of the pass PMOS device .
When Vo < 0.8 V , Vref is still 1.2 V , and Vss =6V

Added after 36 minutes:

Would anyone give me any clues ?

Added after 39 minutes:

The current limit is by monitoring the voltage of the gate of the pass device (the node of C as the picture shown) . It is not by current sense of resistor .

Any one has the experiece of this kind of current limiter ?

need u help on this current limit analysis

I have ever designed LDO by using a scaled down PMOS to sense the current not resistor to sense it.
The sensing pmos monitor the gate of pass pmos to get the ratio current of loading current. I haven't seen the current sense of your circuit.

Does anyone have the expperience on this kind of current limiter ?

Re: need u help on this current limit analysis

Maybe the circuit has some problem . If so , can u tell me ?

Re: need u help on this current limit analysis

So , is there anyone has the experience on the design of current limiter ?

Re: need u help on this current limit analysis

I am still waiting for any help

Re: need u help on this current limit analysis

Maybe there are soma nature transistors or low threshold transistors in the
circuit . Or the Pass device has special sturcture(parasitical structure) that has current sense or current limit ?

What is the purpose of M2 , M8 ?

Re: need u help on this current limit analysis

Maybe the diode-connected MOS transistor should
be other device , such as bipolar transistor ?

Maybe the diode-connected MOS transistor should
be other device , such as bipolar transistor ?