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Logic-BIST's test coverage ?

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joe2moon

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ANY one ever uses the Logic-BIST tool ?

How about the quality ?
For example, the test coverage and the hardware overhead.
------------------------------------------------------------------

Mentor Graphics: LBISTArchitect
Syntest: TurboBIST-Logic
LogicVision: Logic BIST
Synopsys: SoCBIST
 

joe2moon said:
ANY one ever uses the Logic-BIST tool ?

How about the quality ?
For example, the test coverage and the hardware overhead.
------------------------------------------------------------------

Mentor Graphics: LBISTArchitect
Syntest: TurboBIST-Logic
LogicVision: Logic BIST
Synopsys: SoCBIST
Click to expand...

you can try mentor LBIST tool.
 

Logic-BIST tools...

Sorry, I do not intend to get/try/benchmark logic-BIST tools.
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I'm just interesting about the level of current technology >>>
in the area of logic-BIST !

If any one has the experience, please share it.
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For example,
which kind of core ?
the size of the block ?
the BIST controller gate count ?
the length of test cycle ?
*** Most imporant of all *** the test coverage ???
:
:
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Thanks in advance :)
 

As I know until now no company have a stable logic-bist tool. The FC is about 85%.
 

justinzhang said:
As I know until now no company have a stable logic-bist tool. The FC is about 85%.
Click to expand...

LogicVision has developed a new Logic Bist tool & analysis tool, which
they claimed can replace the old and hard-debugging scan DFT. they also
claimed the freq of test clk can be as high as working freq.
 

BIST applies random vectors to your design so its generally about 85% or so. Some vendors add flip-flops to your design to increase test coverage. They look at the untested faults left in your design and add the flip-flops where they provide the most coverage. The problem is that you can add a lot of FFs to your design.

The tests can be applied at a high frequency. However unless you can shift your scan chain at that frequency your tests will not run significantly faster.
 

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