Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about synchronizing FIFO

Status
Not open for further replies.

microe_victor

Junior Member level 2
Joined
Nov 18, 2006
Messages
22
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,283
Activity points
1,443
A asynchronous FIFO requires synchronizing the write_pointer and read_pointer to the other clock domain for compare.
69_1169521836.GIF


we compare syn_read_pointer and write_pointer to generate "full signal" , but the syn_read_pointer is not "latest" but 2 clock cycles before . so the "full signal" will be announced for the extral 2 cycles

Do this effect the efficiency of the fifo ? or do I misunderstand something?

please make some comments. thank you
 

Re: [help] FIFO

1)FIFO full occurs when the write pointer catches up to the synchronized and sampled read pointer. The synchronized
and sampled read pointer might not reflect the current value of the actual read pointer
but the write pointer will not
try to count beyond the synchronized read pointer value. Overflow will not occur.

2)FIFO empty occurs when the read pointer catches up to the synchronized and sampled write pointer. The
synchronized and sampled write pointer might not reflect the current value of the actual write pointer
but the read
pointer will not try to count beyond the synchronized write pointer value. Underflow will not occur


--- subbu.

Added after 20 minutes:

Mr. microe_victor ,

Can i get the document which u have copied over there.

subbu.
 

[help] FIFO

THe write and Read pointers are in different clock domine.
atleast 2 clock cyles are consumed my synchronising circuit to pass the pointer from one clock doming to other clock doming.

So a pointer in a write domine takes 2 clock cycles of read clock to be in read clock domine
 

Re: [help] FIFO

subramanyam said:
1)FIFO full occurs when the write pointer catches up to the synchronized and sampled read pointer. The synchronized
and sampled read pointer might not reflect the current value of the actual read pointer
but the write pointer will not
try to count beyond the synchronized read pointer value. Overflow will not occur.

2)FIFO empty occurs when the read pointer catches up to the synchronized and sampled write pointer. The
synchronized and sampled write pointer might not reflect the current value of the actual write pointer
but the read
pointer will not try to count beyond the synchronized write pointer value. Underflow will not occur


--- subbu.

Added after 20 minutes:

Mr. microe_victor ,

Can i get the document which u have copied over there.

subbu.


Thank you ,
I agree with you that the "overflow" and "underflow" will not happen, actually I am thinking of the efficiency of the FIFO,

If the depth of the fifo is 8, the write clock is the same with read clock.(this is just for a simple instance, but we still have the synchronous FF)
we have 16 data to write. if we read data at "clock cycle 8" , are there any data missing ?

80_1169549562.GIF



here is the paper you want , have fun!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top