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DELAY SUBROUTINE in VHDL

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scorrpeio

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I want to write delay subroutine using VHDL for stepper motor control. The inst- "wait" is not working in "process()". Can anybody help me?
THANK YOU in advance.
 

Do you want to write synthesizable stepper motor contoller??
Or you just need a code for simulation??
wait statement will work in process with null sensitivity list.
and is not synthesizable. You can use counters for delay in
synthesizable code.
 

Hi,

VHDL is a language for synthesis and simulation. You shoud know what kind of instructions are used for synthesis and what kind of instruction are used for simulation.
As the nand_gates said, you can design a counter for generating the delay signal.
 

Here is sample code along with basic testbench.
Hope this helps!

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity stepper_cntl is
  
  port (
    rst_n    : in  std_logic;
    clk    : in  std_logic;             -- system clock lets say 50Mhz
    div    : in  std_logic_vector(7 downto 0);  -- division factor to generate
                                                -- steppermotor clock = 50Mhz/2*div
    dir    : in  std_logic;             -- direction control 
    ph_a   : out std_logic;             -- phase A out
    ph_a_n : out std_logic;             -- phase A invert out
    ph_b   : out std_logic;             -- phase B out 
    ph_b_n : out std_logic);            -- phase B invert out 

end stepper_cntl;

architecture behave of stepper_cntl is
signal count : std_logic_vector(7 downto 0);
signal zero : std_logic;
signal state, state_nx : std_logic_vector(1 downto 0);
begin  -- behave
  ph_a   <= state(1);
  ph_a_n <= not state(1);
  ph_b   <= state(0);
  ph_b_n <= not state(0);
  
  with count select
    zero <=
    '1' when "00000000",
    '0' when others;
  
clock_divider: process (clk, rst_n)
begin  -- process clock_divider
  if rst_n = '0' then                     -- asynchronous reset (active low)
    count <= (others => '0');
  elsif clk'event and clk = '1' then    -- rising clock edge
      if zero = '1' then
        count <= div;
      else
        count <= count - 1;    
      end if;
  end if;
end process clock_divider;
  
phase_gen: process (clk, rst_n)
begin  -- process phase_gen
  if rst_n = '0' then                   -- asynchronous reset (active low)
    state <= (others => '0');
  elsif clk'event and clk = '1' then    -- rising clock edge
      if zero = '1' then
        state <= state_nx;    
      end if;
  end if;
end process phase_gen;

process (state, dir)
begin  -- process
  case state is
    when "00" => if dir = '1' then
                   state_nx <= "01";
                 else
                   state_nx <= "10";
                 end if;
                 
    when "01" => if dir = '1' then
                   state_nx <= "11";
                 else
                   state_nx <= "00";
                 end if;
                 
    when "11" => if dir = '1' then
                   state_nx <= "10";
                 else
                   state_nx <= "01";
                 end if;
                 
    when "10" => if dir = '1' then
                   state_nx <= "00";
                 else
                   state_nx <= "11";
                 end if;
                 
    when others => state_nx <= state;
  end case;
end process;
  
end behave;

Testbench ...
Code: 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity stepper_cntl_tb is

end stepper_cntl_tb;

-------------------------------------------------------------------------------

architecture test of stepper_cntl_tb is

  component stepper_cntl
    port (
      rst_n  : in  std_logic;
      clk    : in  std_logic;
      div    : in  std_logic_vector(7 downto 0);
      dir    : in  std_logic;
      ph_a   : out std_logic;
      ph_a_n : out std_logic;
      ph_b   : out std_logic;
      ph_b_n : out std_logic);
  end component;

  signal rst_n_i  : std_logic := '0';
  signal clk_i    : std_logic := '0';
  signal div_i    : std_logic_vector(7 downto 0) := "10000000";
  signal dir_i    : std_logic := '0';
  signal ph_a_i   : std_logic;
  signal ph_a_n_i : std_logic;
  signal ph_b_i   : std_logic;
  signal ph_b_n_i : std_logic;

begin  -- test
  clk_i <= not clk_i after 10 ns;
  
  DUT: stepper_cntl
    port map (
      rst_n  => rst_n_i,
      clk    => clk_i,
      div    => div_i,
      dir    => dir_i,
      ph_a   => ph_a_i,
      ph_a_n => ph_a_n_i,
      ph_b   => ph_b_i,
      ph_b_n => ph_b_n_i);

process
  begin  -- process
  wait for 100 ns;
  rst_n_i <= '1';
  wait for 50000 ns;
  dir_i <= '1';
  wait for 50000 ns;
  wait;
  end process;  

end test;

-------------------------------------------------------------------------------
 

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