jason_tian
Junior Member level 2
dear all:
the difficulty is the input figures varies over a larg range,so I plan to convert them into remainders of 2pi to confine them in [0,2pi], and then feed the remainders into lookup table. I wonder if I could make a remainder in one clock cycle somehow. and how many cycles does a '%' calculation need in Verilog_HDL?
the difficulty is the input figures varies over a larg range,so I plan to convert them into remainders of 2pi to confine them in [0,2pi], and then feed the remainders into lookup table. I wonder if I could make a remainder in one clock cycle somehow. and how many cycles does a '%' calculation need in Verilog_HDL?