Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Error Amplifier Design

Status
Not open for further replies.
Willt

Willt

Member level 5
Joined
Mar 17, 2006
Messages
83
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Location
Hong Kong
Activity points
2,077
Hi friends,

I want to design an error amplifier for PWM dc-dc boost converter.
It only drives capacitive load so I think OTA is needed.

(1) How much should the gain be?
How does the gain affect the performance? Line regulation? Load regulation?
Or something else?

(2) The frequency of the clock in the converter is 1MHz.
How much should the UGF be?

The answers in above questions will affect the topology I use for the error amplifier. Is it the flow to design amplifier?

Your comment is highly appreciated.

Will
 

UGF must be less than 20% of switching frequency.

Added after 3 minutes:

OTA Gain 60dB, Large UGF will get better Line and Load transenit response.
 

    Willt

    Willt

    Points: 2
    Helpful Answer Positive Rating
Hi Mark,

Thanks for your information.
Now I know that UGF should be 20% less than the switching frequency.

Is the UGF close-loop or open-loop?

Will
 

can you derive how you come up with 20%?

large gain will give you better DC response. i believe UGF is measured at open-loop.
 

Willt said:
Hi friends,

I want to design an error amplifier for PWM dc-dc boost converter.
It only drives capacitive load so I think OTA is needed.

(1) How much should the gain be?
How does the gain affect the performance? Line regulation? Load regulation?
Or something else?

(2) The frequency of the clock in the converter is 1MHz.
How much should the UGF be?

The answers in above questions will affect the topology I use for the error amplifier. Is it the flow to design amplifier?

Your comment is highly appreciated.

Will
Click to expand...

larger gain is better for accuracy and larger gain will reduce the output impedance in closed loop configuration which will reduce the ripple. But be careful, higher gain will give you stability issue, ideally 60db is good enough.
 

If the UGF is so small, can that opamp response quickly?
 

larger gain is better but larger gain reduce the bandwidth then 60-70 is good
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top