amic
Member level 5
Hi. I am new to PLL but have some background in control systems. I am trying to do some PLL simulations to get a quick feel of PLL functinality and stability. For the step response, I am applying a step input at the input ( Fref) and observe the transient voltage at the input of VCO.
The CVO input seems to settle for a while and rings again before settling finally after around 6uS. How do I analyse this? What does this means exactly. Ideally, I was expecting the voltage to remain constant after settling.
could anybody put some light on this?
The CVO input seems to settle for a while and rings again before settling finally after around 6uS. How do I analyse this? What does this means exactly. Ideally, I was expecting the voltage to remain constant after settling.
could anybody put some light on this?
