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HI,
The DIBL is dominating short channel effect in deep submicron technology
For biasing the mosfet, we generally connect the Drain to Vdd(NMOS) and source to Gnd and applying inputs to Gate and substrate to ground. The gate is applied with a +ve voltage, which eventually starts depleting the channel and forming the inversion region under the gate in the channel region. This happens due to Electric field which is acting in the channel region, there is also elcetric field effect perpedicular to the gate field, which is due to the effect of drain bias. In long channel this effect is insignificant, where as in short channel the source and drain come closer and the horizontal field starts effecting thus lowering the barrier in the channel. This leads to increased leakage in the subthreshold region.
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