Sin & Cos algorithm

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine_cos is

  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    en    : in  std_logic;
    sine  : out std_logic_vector(7 downto 0);
    cos   : out std_logic_vector(7 downto 0));

end sine_cos;
architecture behave_sine_cos of sine_cos is
signal sine_r, cos_r	: std_logic_vector(7 downto 0);
signal si, co					: std_logic_vector(7 downto 0);
begin  -- behave_sine_cos
 si <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3));
 co  <= cos_r - (si(7) & si(7) & si(7) & si(7 downto 3));

registers: process (clk, reset)
begin  -- process registers
  if reset = '0' then                   -- asynchronous reset (active low)
    sine_r <= "00000000";
    cos_r <= "01111000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    if (en = '1') then
      sine_r <= si;
      cos_r <= co;
    end if;
  end if;
end process registers;

	sine <= si;
	cos <= co;
end behave_sine_cos;