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1) Multiply by 2, use a DLL (DCM) in a Xilinx part
2) Divide by 9, use two 1/3 dividers in cascade:
To divide by 3 with 50% duty cycle you need:
2FFs and some gates, there is an App in Xilinx about how to do a divider by 3 in a CLB (2FFs and a LUT for some old Xilinx families), search for it, hopefully is still there.
So with: 1 DLL + 4FFs + 2 LUTs you have a 4.5 divider.
I have never tested or tried but it should work.
If you need the divide by 3 circuit give me a shout but googling you should be able to find it.
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