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Verilog case and if else

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ikru26

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if we use a

1)if and else if statement in verilog for generating a multiplexer and synthesize the code
what will be the output looks like..

will it be a priority encoder or a Mux.

2) Do we need to declare the output of a assignment statement as wire incase of a combinational circuit

3) Do we need to declare the output of a assignment statement ( non blocking ) of a sequential circuit
 

1)if and else may result in priority encoder or mux.
that depends upon no of branches u have.
2)no need to declare as wire.
3)u have to declare as reg.
 

1)if the case items in a case are mutualy exclusive then it will form a mux,otherwise it will form priority structure
2)declare it as wire
3)declare as reg
 

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