Test bench and code for 16-bit BCD adder

library ieee;
use ieee.std_logic_1164.all;
 -- Full adder component used in the 4-bit by 4-bit adder
entity adder is
  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    sum  : out std_logic;
    cout : out std_logic);

end adder;
architecture dataflow of adder is

begin  -- dataflow
  sum <= a xor b xor cin;
  cout <= (a and b) or (a and cin) or (b and cin); 
end dataflow;

library ieee;
use ieee.std_logic_1164.all;
use work.all;
-- 4-bit BCD adder component used in the 16-bit BCD adder
entity bcd_adder_4 is
  port (
    a    : in  std_logic_vector(3 downto 0);
    b    : in  std_logic_vector(3 downto 0);
    cin  : in  std_logic;
    sum  : out std_logic_vector(3 downto 0);
    cout : out std_logic);

end bcd_adder_4;

architecture struct of bcd_adder_4 is
component adder
  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    sum  : out std_logic;
    cout : out std_logic);
end component;
signal c : std_logic_vector(4 downto 1);
signal bin_sum : std_logic_vector(3 downto 0);
begin  -- struct
  add0 : adder port map (a(0), b(0), cin , bin_sum(0), c(1)); 
  add1 : adder port map (a(1), b(1), c(1), bin_sum(1), c(2));
  add2 : adder port map (a(2), b(2), c(2), bin_sum(2), c(3));
  add3 : adder port map (a(3), b(3), c(3), bin_sum(3), c(4));
  sum(0) <= bin_sum(0);
  sum(1) <= ((not bin_sum(3) and bin_sum(1) and not c(4)) or (bin_sum(3) and bin_sum(2)
          and not bin_sum(1)) or (bin_sum(0) and c(4)));
  sum(2) <= ((not bin_sum(3) and bin_sum(2)) or (bin_sum(2) and bin_sum(1)));
  sum(3) <= ((bin_sum(3) and not bin_sum(2) and not bin_sum(1)) or (bin_sum(1) and c(4)));
  cout <= ((bin_sum(3) and bin_sum(1)) or (bin_sum(3) and bin_sum(2)) or c(4) );
end struct;

library ieee;
use ieee.std_logic_1164.all;
use work.all;
--structural description 16-bit BCD adder using 4-bit BCD adder
entity bcd_adder_16 is
  port (
    a    : in  std_logic_vector(15 downto 0);
    b    : in  std_logic_vector(15 downto 0);
    cin  : in  std_logic;
    sum  : out std_logic_vector(15 downto 0);
    cout : out std_logic);
end bcd_adder_16;

architecture struct_16 of bcd_adder_16 is
component bcd_adder_4
  port (
    a    : in  std_logic_vector(3 downto 0);
    b    : in  std_logic_vector(3 downto 0);
    cin  : in  std_logic;
    sum  : out std_logic_vector(3 downto 0);
    cout : out std_logic);
end component;
signal t : std_logic_vector(2 downto 0);
begin  -- struct
   f1 : bcd_adder_4 port map (a(3 downto 0),   b(3 downto 0),   cin , sum(3 downto 0),   t(0) );
   f2 : bcd_adder_4 port map (a(7 downto 4),   b(7 downto 4),   t(0), sum(7 downto 4),   t(1) );
   f3 : bcd_adder_4 port map (a(11 downto 8),  b(11 downto 8),  t(1), sum(11 downto 8),  t(2) );
   f4 : bcd_adder_4 port map (a(15 downto 12), b(15 downto 12), t(2), sum(15 downto 12), cout );
end struct_16;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity bcd_adder_16_tb is

end bcd_adder_16_tb;
architecture test of bcd_adder_16_tb is

  component bcd_adder_16
    port (
      a    : in  std_logic_vector(15 downto 0);
      b    : in  std_logic_vector(15 downto 0);
      cin  : in  std_logic;
      sum  : out std_logic_vector(15 downto 0);
      cout : out std_logic);
  end component;

  signal a_i    : std_logic_vector(15 downto 0);
  signal b_i    : std_logic_vector(15 downto 0);
  signal cin_i  : std_logic;
  signal sum_i  : std_logic_vector(15 downto 0);
  signal cout_i : std_logic;
  signal done : boolean := false;  -- flag set when simulation finished
begin  -- test

  DUT: bcd_adder_16
    port map (
      a    => a_i,
      b    => b_i,
      cin  => cin_i,
      sum  => sum_i,
      cout => cout_i);

  read_file : process    -- read file_io.in (one time at start of simulation)
      file my_input : TEXT is in "stimuls.txt";
      variable my_line : LINE;
      variable tmp_a : std_logic_vector(15 downto 0);
      variable tmp_b : std_logic_vector(15 downto 0);
      variable tmp_cin : std_logic_vector(1 downto 0);
      variable cout_check : std_logic_vector(1 downto 0);
      variable sum_check  : std_logic_vector(15 downto 0);
      variable ch : character;
    begin
      loop
        exit when endfile(my_input);
        readline(my_input, my_line);
        -- process input, possibly set up signals or arrays
        read(my_line, tmp_a);
        read(my_line, ch);
        read(my_line, tmp_b);
        read(my_line, ch);  
        read(my_line, tmp_cin);
        read(my_line, ch);
        read(my_line, cout_check);
        read(my_line, ch);
        read(my_line, sum_check);  
        a_i <= tmp_a;
        b_i <= tmp_b;
        cin_i <= tmp_cin(0);
        wait for 2 ns;
        --check sum
        assert sum_i = sum_check report "Test Failed..." severity FAILURE;  
        -- check carry out
        assert cout_i = cout_check(0) report "Test Failed..." severity FAILURE;
      end loop;
      wait; -- one shot at time zero,
    end process read_file;

end test;

0000000000000000 0000000000000000 01 00 0000000000000001
0000000000010000 0000000000010000 00 00 0000000000100000
0000100110011001 1001000000000000 00 00 1001100110011001
1001000000000000 0000100110011001 01 01 0000000000000000