hrkhari
Full Member level 4
Hai Guys:
I had designed an error amplifier for dc biasing purpose. The stability of the design shown in plot (Stb1.jpg) and plot(Stb2.jpg), are in the range of 60-90 degrees in terms of the phase margin. But I had also been informed that the zero and the second pole shouldn't be located nearby each other to avoid roll off. I would appreciate if you could comment on both of the phase margin plot given and shed me some light on the best architecture to choose based on the attached stability plot. Thanks in advance
Rgds
I had designed an error amplifier for dc biasing purpose. The stability of the design shown in plot (Stb1.jpg) and plot(Stb2.jpg), are in the range of 60-90 degrees in terms of the phase margin. But I had also been informed that the zero and the second pole shouldn't be located nearby each other to avoid roll off. I would appreciate if you could comment on both of the phase margin plot given and shed me some light on the best architecture to choose based on the attached stability plot. Thanks in advance
Rgds
