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  1. #1
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    ml403 datasheet

    Hi all,

    I am a student. I am new to verilog and FPGA.
    I have a question.


    How do I use the 16x2 LCD which is on the development board?
    I have a verilog code which I want the LCD to load the ASCII char from
    the verilog code I written. The verilog code is just a few shift
    register acting like a LUT (look up table).


    Is there any way i can control the 16x2 LCD or is there any macro?


    I realize that the LCD i/o is connected to the GPIO so is there any way
    i can use the on board LCD and how?


    Thanks in advance.

    •   Alt6th December 2006, 16:52

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    ml403 lcd

    first you need to get data spec for LCD to figure timing and comand sequence for the LCD.
    Then you have to decide how and to what you will interface you LCD. For example you use Picoblze CPU from Xilinx and execute code on it (regular software) or interface to RS232 so you LCD will display char from the serial port

    good lack



  3. #3
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    xilinx lcd

    Hi Iouri,

    Thanks for the help.

    I know the initilzation for the LCD.
    The LCD is embedded on the development board, ML403 and from the data sheet, it is connected to GPIO, which i don't know hw to access these I/Os. Some of the on board LEDs have pins assigned to them so i know how to turn on and off the LEDs. But for the GPIO, i have no idea how to access them.

    And I just want to control the LCD through the verilog code which i will be program it into the Virtex-4. So i don't think i will be using the Picoblze CPU or RS232.

    Is there a way which i can access the LCD just simply through the verilog coding?



    •   Alt6th December 2006, 17:15

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  4. #4
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    lcd virtex

    That LCD is somewhat awkward. You will definitely need the Lumex data sheets:
    http://www.lumex.com/spec.asp?p_n=LCM-S01602DTR/B
    http://www.lumex.com/MstrCatalog/24_lcd_information.pdf

    Here is a crude quick-and-dirty module that displays "Hello world!"
    Code:
    // synthesis attribute STEPPING top "ES"
    module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
                        parameter       n = 27;
                        parameter       k = 17;
      (* LOC="AE14" *)  input           clk;    // synthesis attribute PERIOD clk "100.0 MHz"
                        reg     [n-1:0] count=0;
                        reg             lcd_busy=1;  // Lumex LCM-S01602DTR/B
                        reg             lcd_stb;
                        reg       [5:0] lcd_code;
                        reg       [6:0] lcd_stuff;
      (* LOC="AC17" *)  output reg      lcd_rs;
      (* LOC="AB17" *)  output reg      lcd_rw;
      (* LOC="AF12" *)  output reg      lcd_7;
      (* LOC="AE12" *)  output reg      lcd_6;
      (* LOC="AC10" *)  output reg      lcd_5;
      (* LOC="AB10" *)  output reg      lcd_4;
      (* LOC="AE13" *)  output reg      lcd_e;
    
      always @ (posedge clk) begin
        count <= count + 1;
        case (count[k+7:k+2])
           0: lcd_code <= 6'b000010;    // function set
           1: lcd_code <= 6'b000010;
           2: lcd_code <= 6'b001100;
           3: lcd_code <= 6'b000000;    // display on/off control
           4: lcd_code <= 6'b001100;
           5: lcd_code <= 6'b000000;    // display clear
           6: lcd_code <= 6'b000001;
           7: lcd_code <= 6'b000000;    // entry mode set
           8: lcd_code <= 6'b000110;
           9: lcd_code <= 6'h24;        // H
          10: lcd_code <= 6'h28;
          11: lcd_code <= 6'h26;        // e
          12: lcd_code <= 6'h25;
          13: lcd_code <= 6'h26;        // l
          14: lcd_code <= 6'h2C;
          15: lcd_code <= 6'h26;        // l
          16: lcd_code <= 6'h2C;
          17: lcd_code <= 6'h26;        // o
          18: lcd_code <= 6'h2F;
          19: lcd_code <= 6'h22;        //
          20: lcd_code <= 6'h20;
          21: lcd_code <= 6'h25;        // W
          22: lcd_code <= 6'h27;
          23: lcd_code <= 6'h26;        // o
          24: lcd_code <= 6'h2F;
          25: lcd_code <= 6'h27;        // r
          26: lcd_code <= 6'h22;
          27: lcd_code <= 6'h26;        // l
          28: lcd_code <= 6'h2C;
          29: lcd_code <= 6'h26;        // d
          30: lcd_code <= 6'h24;
          31: lcd_code <= 6'h22;        // !
          32: lcd_code <= 6'h21;
          default: lcd_code <= 6'b010000;
        endcase
        if (lcd_rw)
          lcd_busy <= 0;
        lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
        lcd_stuff <= {lcd_stb,lcd_code};
        {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
      end
    endmodule
    PicoBlaze is a cute little processor. Check it out someday.


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  5. #5
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    ml403çš„lcd

    hey echo47, ive seen this for the first time

    Code:
    (* LOC="AC17" *)
    is this something new? do you need to make a ucf file after assigning pins like this? how do you assign pins to bus using this method?



    •   Alt7th December 2006, 04:45

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    ml403 schematic

    If you define synthesis constraints in your HDL, you don't need to put them into a UCF. However, some Xilinx constraints don't work in HDL (an ISE or XST limitation I guess). The Constraints Guide explains which ones work in HDL, and gives syntax examples.

    These two ISE XST attributes are equivalent. The first one is Verilog, the second one is Verilog 2001:
    Code:
    output reg lcd_rs; // synthesis attribute LOC lcd_rs "AC17";
    
    (* LOC="AC17" *) output reg lcd_rs;
    I like the second form because I don't have to specify the signal name (so it works in a "generate" block), but unfortunately the attribute must precede the declaration, and that looks ugly - it messes up my indenting!

    Or if you want to define a bus pinout:
    Code:
    input [3:0] rxd; // synthesis attribute LOC rxd "C4,D4,E1,F1";
    
    (* LOC="C4,D4,E1,F1" *) input [3:0] rxd;
    The Verilog 2001 syntax allows multiple attributes. Very nice! Example:
    Code:
    (* LOC="SLICE_X1Y0:SLICE_X1Y63",BEL="XORF" *) XORCY_L blah blah blah ;



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    vhdl code lcd 16x2

    Thanks echo47.

    That is what i wanted.

    By the way, I am curious about where you find the coding and the location for the pins connected to the LCD. Because what i found in the data sheet of ML403, i only saw that the pins are connected to the GPIO and never mentioned about the location on the fpga.

    Anyway thank you very much for your help.



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    ml403 ucf

    The ML403 user manuals don't say much about the LCD. I found the LCD pin connections on the ML403 schematic, sheets 2 and 12:
    http://www.xilinx.com/products/boards/ml403/docs.htm

    I wrote that Verilog code myself after reading the ML403 schematic and the Lumex data sheets. My example code is very crude, so please write better code for yourself!


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    Re: Xilinx Virtex-4 ML403 16x2 LCD

    Hello all!

    I know it is quite late messaging on this thread...

    But can any body explain me the ENABLE sequence of this code.

    I have understood almost the complete code using the data sheet, and also I understand the enable pin working, but how is this wokring here in this code, this I cannot understand .

    I will be really grateful if some one who has done this code can reply
    When the going gets weird, the weird turn pro.
    H.S. Thompson



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    Re: lcd virtex

    Hi,

    Thanks for the code it was really helpful to me.

    Can u tell how to access the 2nd line of the lcd using verilog, and why does the function set in the below code is for 3 counts?... can u reply with a code for sending 2 lines of data on to the lcd.


    Thanks in advance
    Mahesh R


    Quote Originally Posted by echo47 View Post
    That LCD is somewhat awkward. You will definitely need the Lumex data sheets:
    http://www.lumex.com/spec.asp?p_n=LCM-S01602DTR/B
    http://www.lumex.com/MstrCatalog/24_lcd_information.pdf

    Here is a crude quick-and-dirty module that displays "Hello world!"
    Code:
    // synthesis attribute STEPPING top "ES"
    module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
                        parameter       n = 27;
                        parameter       k = 17;
      (* LOC="AE14" *)  input           clk;    // synthesis attribute PERIOD clk "100.0 MHz"
                        reg     [n-1:0] count=0;
                        reg             lcd_busy=1;  // Lumex LCM-S01602DTR/B
                        reg             lcd_stb;
                        reg       [5:0] lcd_code;
                        reg       [6:0] lcd_stuff;
      (* LOC="AC17" *)  output reg      lcd_rs;
      (* LOC="AB17" *)  output reg      lcd_rw;
      (* LOC="AF12" *)  output reg      lcd_7;
      (* LOC="AE12" *)  output reg      lcd_6;
      (* LOC="AC10" *)  output reg      lcd_5;
      (* LOC="AB10" *)  output reg      lcd_4;
      (* LOC="AE13" *)  output reg      lcd_e;
    
      always @ (posedge clk) begin
        count <= count + 1;
        case (count[k+7:k+2])
           0: lcd_code <= 6'b000010;    // function set
           1: lcd_code <= 6'b000010;
           2: lcd_code <= 6'b001100;
           3: lcd_code <= 6'b000000;    // display on/off control
           4: lcd_code <= 6'b001100;
           5: lcd_code <= 6'b000000;    // display clear
           6: lcd_code <= 6'b000001;
           7: lcd_code <= 6'b000000;    // entry mode set
           8: lcd_code <= 6'b000110;
           9: lcd_code <= 6'h24;        // H
          10: lcd_code <= 6'h28;
          11: lcd_code <= 6'h26;        // e
          12: lcd_code <= 6'h25;
          13: lcd_code <= 6'h26;        // l
          14: lcd_code <= 6'h2C;
          15: lcd_code <= 6'h26;        // l
          16: lcd_code <= 6'h2C;
          17: lcd_code <= 6'h26;        // o
          18: lcd_code <= 6'h2F;
          19: lcd_code <= 6'h22;        //
          20: lcd_code <= 6'h20;
          21: lcd_code <= 6'h25;        // W
          22: lcd_code <= 6'h27;
          23: lcd_code <= 6'h26;        // o
          24: lcd_code <= 6'h2F;
          25: lcd_code <= 6'h27;        // r
          26: lcd_code <= 6'h22;
          27: lcd_code <= 6'h26;        // l
          28: lcd_code <= 6'h2C;
          29: lcd_code <= 6'h26;        // d
          30: lcd_code <= 6'h24;
          31: lcd_code <= 6'h22;        // !
          32: lcd_code <= 6'h21;
          default: lcd_code <= 6'b010000;
        endcase
        if (lcd_rw)
          lcd_busy <= 0;
        lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
        lcd_stuff <= {lcd_stb,lcd_code};
        {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
      end
    endmodule
    PicoBlaze is a cute little processor. Check it out someday.



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    Re: lcd virtex

    hi, can any one give me any link or document regarding virtex 4,x it it urgent for me to learn it as soon as possible.

    please HELP ME :(



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    Re: lcd virtex

    Quote Originally Posted by echo47 View Post
    That LCD is somewhat awkward. You will definitely need the Lumex data sheets:
    http://www.lumex.com/spec.asp?p_n=LCM-S01602DTR/B
    http://www.lumex.com/MstrCatalog/24_lcd_information.pdf

    Here is a crude quick-and-dirty module that displays "Hello world!"
    Code:
    // synthesis attribute STEPPING top "ES"
    module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
                        parameter       n = 27;
                        parameter       k = 17;
      (* LOC="AE14" *)  input           clk;    // synthesis attribute PERIOD clk "100.0 MHz"
                        reg     [n-1:0] count=0;
                        reg             lcd_busy=1;  // Lumex LCM-S01602DTR/B
                        reg             lcd_stb;
                        reg       [5:0] lcd_code;
                        reg       [6:0] lcd_stuff;
      (* LOC="AC17" *)  output reg      lcd_rs;
      (* LOC="AB17" *)  output reg      lcd_rw;
      (* LOC="AF12" *)  output reg      lcd_7;
      (* LOC="AE12" *)  output reg      lcd_6;
      (* LOC="AC10" *)  output reg      lcd_5;
      (* LOC="AB10" *)  output reg      lcd_4;
      (* LOC="AE13" *)  output reg      lcd_e;
    
      always @ (posedge clk) begin
        count <= count + 1;
        case (count[k+7:k+2])
           0: lcd_code <= 6'b000010;    // function set
           1: lcd_code <= 6'b000010;
           2: lcd_code <= 6'b001100;
           3: lcd_code <= 6'b000000;    // display on/off control
           4: lcd_code <= 6'b001100;
           5: lcd_code <= 6'b000000;    // display clear
           6: lcd_code <= 6'b000001;
           7: lcd_code <= 6'b000000;    // entry mode set
           8: lcd_code <= 6'b000110;
           9: lcd_code <= 6'h24;        // H
          10: lcd_code <= 6'h28;
          11: lcd_code <= 6'h26;        // e
          12: lcd_code <= 6'h25;
          13: lcd_code <= 6'h26;        // l
          14: lcd_code <= 6'h2C;
          15: lcd_code <= 6'h26;        // l
          16: lcd_code <= 6'h2C;
          17: lcd_code <= 6'h26;        // o
          18: lcd_code <= 6'h2F;
          19: lcd_code <= 6'h22;        //
          20: lcd_code <= 6'h20;
          21: lcd_code <= 6'h25;        // W
          22: lcd_code <= 6'h27;
          23: lcd_code <= 6'h26;        // o
          24: lcd_code <= 6'h2F;
          25: lcd_code <= 6'h27;        // r
          26: lcd_code <= 6'h22;
          27: lcd_code <= 6'h26;        // l
          28: lcd_code <= 6'h2C;
          29: lcd_code <= 6'h26;        // d
          30: lcd_code <= 6'h24;
          31: lcd_code <= 6'h22;        // !
          32: lcd_code <= 6'h21;
          default: lcd_code <= 6'b010000;
        endcase
        if (lcd_rw)
          lcd_busy <= 0;
        lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
        lcd_stuff <= {lcd_stb,lcd_code};
        {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
      end
    endmodule
    PicoBlaze is a cute little processor. Check it out someday.
    if (lcd_rw)
    lcd_busy <= 0;
    lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
    lcd_stuff <= {lcd_stb,lcd_code};
    {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;

    can you tell me how this part work? i have understode the remaing but couldn't figure out this part work, please if you can tell me i will be great full to you.



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