If you define synthesis constraints in your HDL, you don't need to put them into a UCF. However, some Xilinx constraints don't work in HDL (an ISE or XST limitation I guess). The Constraints Guide explains which ones work in HDL, and gives syntax examples.
These two ISE XST attributes are equivalent. The first one is Verilog, the second one is Verilog 2001:
I like the second form because I don't have to specify the signal name (so it works in a "generate" block), but unfortunately the attribute must precede the declaration, and that looks ugly - it messes up my indenting!
output reg lcd_rs; // synthesis attribute LOC lcd_rs "AC17";
(* LOC="AC17" *) output reg lcd_rs;
Or if you want to define a bus pinout:
The Verilog 2001 syntax allows multiple attributes. Very nice! Example:
input [3:0] rxd; // synthesis attribute LOC rxd "C4,D4,E1,F1";
(* LOC="C4,D4,E1,F1" *) input [3:0] rxd;
(* LOC="SLICE_X1Y0:SLICE_X1Y63",BEL="XORF" *) XORCY_L blah blah blah ;