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Simulation using modelSim

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Elnegm

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Hi
I'm abeginner with verilog and i use FPGA advantage and modelSim
when i want to simulate the following code output counte give me unknown
Is there is setting in ModelSim i have to set in order to simulate correctly?
Code: 
module firstseq (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
always @ (negedge clk)
if (reset == 1'b1)
count <= 0;
else if ( enable == 1'b1)
count <= count + 1;
endmodule
 

Not realy. All you need to do: do the tutorial execise (it is comming with you modelsim instalation) and you will figure out what to do


regards,
 

Just force the value desired in put and u can see the response.. Go to edit tab in signals window and force 1 or 0 in that place and run u will get the response.. for clk there is a seperate force value for clock in the edit tab...

nothing to do with the settignsg
 

To simulate this code you have to procedures:
1- Create a verilog test bench to stimulate the inputs
2- Use "force" commands from ModelSim to put your module in action
 

it's exactly like yasser said
but i would advice forcing signals cause the design is simple
also try to begin by reseting the circuit
and be sure that the clock frequency is chosen correctly in comparison with ur other signals
 

Write TB
module firstseq_tb ;
reg clk, reset, enable;
wire [3:0] count;
firstseq d1(clk, reset, enable, count);
always
#2 clk =~clk;
initial clk=0;
initial
begin
enable =1'b1; reset=0;
#4 reset=1'b1;
#and so on.........
end
endmodule
Thanks
 

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